Semiconductor Memory Verification Voltage Segmentation
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in performing write operations at high speeds due to high current consumption during verification operations, as they typically charge all bit lines during verification, which is inefficient and consumes excessive power.
Innovation Solution
The semiconductor memory device employs a controller that applies specific verification voltages to word lines and bit lines in a program loop, with only necessary bit lines being charged for each verification level, allowing for sequential verification and reducing current consumption by optimizing the sense amplifier module's operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all bit lines are charged during verification operation, then verification accuracy is improved, but current consumption increases
Solution Approach 1:
The patent segments the verification process into multiple verification operations corresponding to different threshold voltage levels. Instead of charging all bit lines simultaneously for a single comprehensive verification, the system performs sequential verifications at different voltage levels, charging only the necessary bit lines for each specific verification level. This segmentation reduces the total number of bit lines charged at any given time while maintaining verification accuracy across all threshold levels.
Solution Approach 2:
The patent applies partial action by charging only the subset of bit lines that are necessary for each specific verification level rather than all bit lines. For example, during verification at a lower threshold voltage level, only bit lines corresponding to memory cells with that specific threshold voltage range are charged, leaving other bit lines uncharged. This partial charging approach maintains sufficient verification accuracy for each level while significantly reducing overall current consumption.
2Productivity
If multiple verification voltages are applied sequentially to word lines, then write operation speed is improved, but operation complexity increases
Solution Approach 1:
The verification process is segmented into multiple independent verification operations, each targeting a specific threshold voltage level. Each verification operation is self-contained and can be executed independently, allowing for systematic management of the verification process. The controller manages each verification operation separately, applying the corresponding verification voltage to the word line and evaluating results before proceeding to the next verification level, thereby improving speed through parallelizable independent operations.
Solution Approach 2:
The patent implements preliminary action by performing verification operations in a predetermined sequence from lower to higher threshold voltage levels. The controller is pre-configured with the verification voltage sequence and executes verifications in this predetermined order. This preliminary planning of the verification sequence allows the system to optimize the operation flow, reduce decision-making complexity during execution, and improve overall write operation speed through systematic progression.
Data Source
AI summary
A semiconductor memory device includes memory cells connected to word lines and bit lines. In a verification operation, a controller applies first and second verification voltages to a word line in sequence, a first voltage to a first bit line of a first cell and a second voltage to second bit line during first level verification, and, if the first cell passes first voltage level verification, the first voltage is then applied to both the first and second bit lines while the second verification voltage is applied to the word line.