Memory Verify Circuit for Adjacent Word Line Retention Control

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Solution Overview

Problem

Nonvolatile memory devices face challenges in maintaining data retention characteristics due to the influence of adjacent word line states during verify operations, which can lead to uneven cell distribution and reduced programming efficiency.

Innovation Solution

A nonvolatile memory device with a verify circuit that controls word line and bit line voltages differently based on the program state of adjacent word lines, allowing for improved retention characteristics without separate read operations, by applying lower voltages to unselected word lines and higher voltages to the bit line during verify operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional verify operations are performed without considering adjacent word line states, then the verify operation can be completed with standard voltage levels, but data retention characteristics deteriorate due to charge loss and uneven cell distribution

Engineering Contradiction:

Improvedata retention characteristicVSAvoidcharge loss

Core Design Contradiction:

ReliabilityVSLoss of energy

Solution Approach 1:

The patent applies different voltage levels to different word lines based on their program state. Specifically, unselected word lines that are in a programmed state receive a different voltage (e.g., lower voltage) compared to unselected word lines in an erased state. This local differentiation of voltage conditions improves retention characteristics by preventing charge loss in programmed cells while maintaining proper verify operation conditions.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent changes the voltage parameter applied to unselected word lines during verify operations based on the program state of adjacent word lines. The verify circuit dynamically adjusts the voltage level (e.g., using Vpass1 for erased word lines and Vpass2 for programmed word lines) to optimize both retention characteristics and programming efficiency. This parameter adaptation resolves the contradiction by preventing charge loss without requiring excessive voltage levels.

Inventive Principle:

Principle #35Parameter changes

2Productivity

If higher voltages are applied to unselected word lines during verify operations, then programming efficiency improves, but retention characteristics worsen due to increased charge loss

Engineering Contradiction:

Improveprogramming efficiencyVSAvoidretention characteristic

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

Inventive Principle:

Principle #35Parameter changes

3Device complexity

If uniform voltage levels are applied to all unselected word lines during verify operations, then the control logic is simplified, but cell distribution becomes uneven leading to reduced programming efficiency

Engineering Contradiction:

Improvecontrol logic complexityVSAvoidprogramming efficiency

Core Design Contradiction:

Device complexityVSProductivity

Solution Approach 1:

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The verify circuit uses feedback from the program state of adjacent word lines to dynamically adjust the voltage applied to unselected word lines. By monitoring whether adjacent word lines are in a programmed or erased state, the verify circuit selects appropriate voltage levels (Vpass1 or Vpass2) to maintain uniform cell distribution and optimize programming efficiency.

Inventive Principle:

Principle #23Feedback

4Measurement precision

If separate read operations are performed to account for adjacent word line states, then accurate verify operations can be performed, but operation time increases

Engineering Contradiction:

Improveverify operation accuracyVSAvoidoperation time

Core Design Contradiction:

Measurement precisionVSLoss of time

Solution Approach 1:

The patent merges the verify operation with the consideration of adjacent word line states by integrating the program state detection and voltage selection logic directly into the verify circuit. This eliminates the need for separate read operations to determine adjacent word line states, as the verify circuit simultaneously performs both functions, thereby maintaining verify accuracy while reducing operation time.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The verify circuit prepares and applies the appropriate voltage levels to unselected word lines before the actual verify operation begins, based on pre-existing program state information. This preliminary voltage adjustment ensures that the verify operation can proceed accurately without requiring additional read operations, thus reducing overall operation time while maintaining precision.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS11869594B2Nonvolatile memory device including a logic circuit to control word and bitline voltages

Publication Date: 2024.01.09 SAMSUNG ELECTRONICS CO LTD

AI summary

A nonvolatile memory device includes a memory cell array, a voltage generator and a control logic circuit for programming a selected memory cell of the memory cell array to a selected word line into a first program state by controlling the voltage generator and a verify operation on the memory cell array. The control logic circuit controls a first word line voltage applied to an adjacent word line not to be programmed in the verify operation to be different from a read voltage level of a read voltage applied in a read operation of the nonvolatile memory and controls a bit line voltage applied to a bit line in the read operation. The control logic circuit controls the voltage generator to apply a plurality of different and decreasing verify voltages to the selected word line in the verify operation.