Memory Cell Program-Verify Skip for Highest Data State
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Solution Overview
Problem
Existing memory apparatuses face inefficiencies in programming time due to the need to verify all data states, which can lead to adverse effects and prolonged operation times.
Innovation Solution
A memory apparatus and method that skips verification of the highest data state in at least one program loop, applying programming pulses followed by verification pulses for other data states, allowing for faster programming by optimizing the verification process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If verification is performed for all data states during programming, then data state accuracy is improved, but programming time increases
Solution Approach 1:
The patent extracts the verification operation for the highest data state from the standard programming sequence. By identifying that the highest data state verification can be performed separately or omitted in certain conditions, the patent removes this time-consuming step from the critical programming path, thereby reducing overall programming time while maintaining sufficient data state accuracy through alternative verification strategies.
Solution Approach 2:
The patent applies partial verification by performing verification operations on only some data states (specifically, excluding the highest data state in certain program loops) rather than verifying all data states. This partial action approach achieves acceptable programming performance by verifying the most critical data states while accepting that the highest data state may require additional verification passes only when necessary.
2Reliability
If verification pulses are applied for all data states in each program loop, then programming reliability is improved, but programming efficiency deteriorates
Solution Approach 1:
The patent introduces dynamic control of the verification process by making the verification behavior adaptive based on programming conditions. The control circuit dynamically determines whether to perform verification for the highest data state in each program loop based on factors such as the current programming stage, data state distribution, and convergence characteristics. This dynamic approach maintains reliability by verifying when necessary while improving efficiency by skipping verification when the programming state indicates it is not needed.
Solution Approach 2:
The patent segments the verification process into different stages or conditions. Instead of uniformly applying verification to all data states in all program loops, the patent divides the programming process into segments where verification for the highest data state is applied selectively. This segmentation allows the system to focus verification resources on critical data states and programming stages, thereby maintaining reliability while reducing overall verification overhead and improving programming efficiency.
Data Source
AI summary
A memory apparatus and operating method are provided. The apparatus includes memory cells connected to word lines and configured to retain a threshold voltage corresponding to data states. The data states includes a highest data state in which the threshold voltage of the memory cells associated therewith is higher than for others of the data states. A control means is configured to apply each of a series of programming pulses of a program voltage followed by verification pulses of a plurality of program verify voltages each associated with one of the data states to selected ones of the word lines to program and verify the memory cells connected thereto during each of a plurality of program loops of a program operation. The control means skips verification of the memory cells targeted for the highest data state in at least one of the plurality of program loops.