Nonvolatile Memory Verify Time Adjustment for CSL Noise
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Nonvolatile flash memory devices face reliability issues due to CSL noise, which causes threshold voltage distributions to widen, leading to errors in read and program operations by misinterpreting on-cells as off-cells.
Innovation Solution
A method and apparatus for a nonvolatile memory device that decodes page addresses to adjust the maximum verify time of program loops, allowing for tailored verify operations to reduce the impact of CSL noise, thereby improving programming efficiency and accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the maximum verify time of program loops is increased to improve programming accuracy and reduce errors caused by CSL noise, then the reliability of read and program operations is improved, but the total programming time increases
Solution Approach 1:
The patent applies local quality by differentiating verify time allocation based on page address types. LSB pages receive shorter verify times while MSB pages receive longer verify times, optimizing the balance between reliability and speed for different data types within the same memory system.
Solution Approach 2:
The patent implements dynamic adjustability of verify time parameters based on real-time detection of page address types. The control logic dynamically selects appropriate verify time values from a set of predetermined values, allowing the system to adapt its programming parameters to specific operational requirements.
2Measurement precision
If the verify operation time is extended to accurately distinguish program states and reduce misinterpretation errors, then the measurement precision of threshold voltage detection is improved, but the duration of program operations increases
Solution Approach 1:
The patent applies local quality by implementing different measurement precision levels for different page types. MSB pages, which are more susceptible to CSL noise, receive extended verify times for higher measurement precision, while LSB pages use standard verify times, thus optimizing precision where most needed without universally increasing operation duration.
3Ease of operation
If uniform verify time is used for all page addresses, then the device complexity is reduced and ease of operation is improved, but the adaptability to different page types affected by CSL noise varies is limited
Solution Approach 1:
The patent implements dynamic adaptability through automatic detection of page address types and selection of appropriate verify time parameters. The control logic dynamically adjusts operation parameters based on the detected page type, providing optimization without requiring manual configuration or complex user intervention.
Solution Approach 2:
The system performs self-service by automatically detecting page address types and selecting optimal verify time parameters without external intervention. The control logic autonomously manages the verification process, adapting to different page types and CSL noise conditions based on inherent system observations.
Data Source
AI summary
A nonvolatile memory device is programmed by decoding a received address, determining whether the received address is a first type of page address or a second type of page address, adjusting a maximum verify time of a program loop used to verify a program state of page data according to the determined type of page address, and performing a verify operation during the adjusted maximum verify time.