Memory Device Verify Timing Optimization
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Solution Overview
Problem
Current memory devices face inefficiencies in program operation performance due to the lack of effective methods for determining the optimal start time for program verify operations across multiple program states, leading to suboptimal verification times and reduced overall performance.
Innovation Solution
A memory device and operating method that include a peripheral circuit and control logic to program memory cells to a target program state, perform program verify operations, and determine the start time for adjacent program states based on the number of memory cells passing or failing the verify operation, ensuring efficient program verify operations by optimizing the timing of higher-ranked program states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If program verify operations are performed sequentially for each program state without optimization, then verification completeness is ensured, but total verification time increases
Solution Approach 1:
The patent applies preliminary action by determining and preparing the start time for program verify operations of higher-ranked program states before actually executing those verify operations. The control logic calculates optimal start times based on bit numbers from lower-ranked states, allowing the system to be ready to immediately initiate verify operations when conditions are met, thereby reducing idle time and improving overall program operation performance
Solution Approach 2:
The patent implements dynamics by making the start time of program verify operations adaptive rather than fixed. The control logic dynamically adjusts the start time of verify operations for higher-ranked program states based on real-time bit number results from verify operations of lower-ranked states. This dynamic timing optimization allows the system to accelerate verify operations when conditions permit while maintaining verification completeness
2Speed
If program verify operations start too early, then verification speed improves, but verification accuracy may be compromised
Solution Approach 1:
The patent applies feedback by using the bit number results from program verify operations of lower-ranked program states to determine the optimal start time for verify operations of higher-ranked states. The control logic continuously monitors verification results and adjusts timing based on this feedback, ensuring that verify operations start at the earliest safe moment when verification accuracy is guaranteed while maximizing verification speed
3Reliability
If program verify operations are delayed to ensure accuracy, then verification reliability improves, but total program operation time increases
Solution Approach 1:
The control logic performs preliminary calculation of optimal start times for program verify operations of higher-ranked program states based on bit numbers from lower-ranked states. This preliminary timing determination allows the system to execute verify operations at the earliest possible moment that guarantees accuracy, minimizing unnecessary delays while maintaining verification reliability
Solution Approach 2:
The patent implements dynamic timing adjustment where the start time of verify operations is not fixed but adaptively determined based on actual bit number results from previous verify operations. This dynamic approach allows the system to shorten verification duration when conditions permit while ensuring accuracy requirements are met, thereby optimizing the balance between reliability and operation duration
Data Source
AI summary
A memory device includes a plurality of memory cells, a peripheral circuit, and a control logic. The peripheral circuit programs the plurality of memory cells to a program state among a plurality of program states. The control logic controls the peripheral circuit to perform a program verify operation for at least one program state among the plurality of program states, counts a bit number having a predetermined logic value by comparing a program verify voltage corresponding to a target program state in the at least one program state in a program verify operation for the target program state with threshold voltages of the plurality of memory cells, and determines a start time of a program verify operation for a program state higher than the target program state among the plurality of program states, based on the bit number having the predetermined logic value.