Non-volatile Memory Verify Voltage Adjustment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional NAND-type flash memory experiences gradual deterioration of gate-insulating film due to repeated write and erase operations, leading to reduced data retention characteristics and increased probability of data misreads, while also having slow write times.
Innovation Solution
A non-volatile semiconductor memory device that includes a memory cell array with a control circuit executing first and second page writing operations, verify operations, and a step-up operation to adjust threshold voltages, along with a sense amplifier circuit to determine data storage by detecting bit line potentials, thereby reducing erroneous reads and shortening write times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If verify read operations are repeated to ensure data write completion, then data retention characteristics are improved, but write time increases
Solution Approach 1:
The patent dynamically adjusts the verify read voltage based on the number of program failures detected. When failures are few, a lower verify voltage is used to speed up verification. When failures are numerous, the verify voltage is increased to ensure accurate detection. This dynamic voltage adjustment resolves the contradiction by adapting the verification process to actual cell states, reducing unnecessary high-voltage verification cycles while maintaining reliability.
Solution Approach 2:
The patent changes the verify read voltage parameter based on program operation results. The control circuit monitors program failures and adjusts the verify voltage accordingly - using lower voltages for successful writes and higher voltages for failed writes. This parameter change strategy reduces the average verification time while ensuring data retention characteristics are maintained for both successful and failed program operations.
2Reliability
If write voltage is increased through step-up operations to complete programming, then data write reliability is improved, but gate-insulating film deteriorates faster
Solution Approach 1:
The patent implements dynamic voltage adjustment where the verify read voltage changes based on program failure counts. This allows the system to use minimal necessary voltage for each verification cycle - lower voltages when programming succeeds and higher voltages only when necessary to detect failures. This dynamic approach improves write reliability while reducing cumulative stress on the gate-insulating film compared to always using high step-up voltages.
Solution Approach 2:
The patent enables the verify operation to proceed efficiently by skipping unnecessary high-voltage verification steps. When program operations succeed, the system uses lower verify voltages and can terminate verification earlier, effectively 'skipping' the time-consuming high-voltage verification cycles. This reduces the total number of high-voltage stress events on the gate-insulating film while maintaining write reliability through targeted high-voltage verification only when needed.
3Quantity of substance
If multi-value storage is implemented to increase capacity, then storage density is improved, but threshold voltage distribution becomes wider
Solution Approach 1:
The patent applies different verify read voltages to different regions of the threshold voltage distribution. By monitoring program failures and adjusting verify voltage locally based on the specific failure mode, the system can accurately distinguish between successfully programmed cells and failed cells even in multi-value storage where threshold voltage distributions overlap. This local quality adjustment maintains manufacturing precision while enabling high storage capacity.
Solution Approach 2:
The patent changes the verify read voltage parameter based on the detected program failure characteristics. For multi-value storage, this allows the system to adaptively select appropriate verify voltages for different threshold voltage regions, ensuring accurate verification across the wider distribution while maintaining the ability to store multiple bits per cell. The parameter change strategy preserves manufacturing precision by using voltage levels tailored to specific threshold voltage ranges.
Data Source
AI summary
In one embodiment, a control circuit executes a first page writing operation, a first verify operations, a second page writing operation, a second verify operations, a step-up operation. The control circuit executes the first page writing operation which forms an intermediate distribution, and a first read operation which reads data form the intermediate distribution by using a determine voltage higher than a first verify voltage with a first value, and changes a second verify voltage based on the result of the first read operation.