Nonvolatile Memory Program Verify Voltage Control

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Solution Overview

Problem

Flash memory devices with multi-level cells face challenges in maintaining a sufficient margin between program states due to wide threshold voltage distributions, affecting data retention and programming accuracy.

Innovation Solution

Implementing a program-verify loop with both pre-verify and target verify operations using a common verify voltage for different programmable states, and adjusting bit-line voltages based on verification results to reduce threshold voltage distribution and enhance programming speed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If multi-level cells are used to increase storage capacity, then storage capacity increases, but threshold voltage distribution becomes wider affecting data retention and programming accuracy

Engineering Contradiction:

Improvestorage capacityVSAvoidprogramming accuracy

Core Design Contradiction:

Quantity of substanceVSManufacturing precision

Solution Approach 1:

The patent segments the verification process into two distinct operations: pre-verify operation for lower programmable states and target verify operation for higher programmable states. This segmentation allows each verify operation to be optimized for its specific state range, improving programming accuracy while maintaining multi-level cell storage capacity.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The pre-verify operation serves as a preliminary action before the target verify operation. By first checking lower states and then proceeding to target state verification, the system ensures more accurate programming by catching intermediate states that would otherwise be missed, thereby reducing threshold voltage distribution width.

Inventive Principle:

Principle #10Preliminary action

2Measurement precision

If separate verify voltages are used for pre-verify and target verify operations, then verification accuracy improves, but device complexity and operation time increase

Engineering Contradiction:

Improveverification accuracyVSAvoidoperation complexity

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The patent merges the pre-verify voltage and target verify voltage into a single common verify voltage that is applied simultaneously to both verify operations. This consolidation reduces device complexity and operation time while maintaining verification accuracy through the segmented verification approach.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The common verify voltage serves multiple functions: it performs both pre-verify operation for lower states and target verify operation for higher states. This multi-functionality eliminates the need for separate voltage generation circuits, reducing device complexity while maintaining the accuracy benefits of separate verify operations.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Reliability

If traditional sequential verify operations are performed, then verification thoroughness is maintained, but programming speed decreases

Engineering Contradiction:

Improveverification thoroughnessVSAvoidprogramming speed

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent combines pre-verify operation and target verify operation into a single simultaneous verification step using a common verify voltage. This merging allows both verification checks to be performed in parallel, significantly increasing programming speed while maintaining the thoroughness of traditional sequential verification through the segmented verification logic.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

By performing both pre-verify and target verify operations simultaneously in a continuous process rather than sequentially, the system maintains verification thoroughness without the time loss associated with sequential operations. The useful action of verification continues uninterrupted while checking multiple states.

Inventive Principle:

Principle #20Continuity of useful action

Data Source

PatentUS8305817B2Nonvolatile memory devices and program methods thereof in which a target verify operation and a pre-pass verify operation are performed simultaneously using a common verify voltage

Publication Date: 2012.11.06 SAMSUNG ELECTRONICS CO LTD

AI summary

Provided are nonvolatile memory devices and program methods thereof. A nonvolatile memory device provides a program voltage to a selected word line and performs a program verify operation. The nonvolatile memory device controls a bit line voltage of the next program loop according to the program verification result. In the program verification operation, a target verify voltage is used as a pre-verify voltage. The nonvolatile memory device controls the bit line voltage of the next program loop according to the program verification result, thus making it possible to reduce the threshold voltage distribution of a memory cell. Also, the nonvolatile memory device uses the target verify voltage as the pre-verify voltage, thus making it possible to increase the program verification speed.