Nonvolatile Memory Verify Voltage Segmentation

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Solution Overview

Problem

Existing nonvolatile semiconductor memory devices, such as NAND flash memories, face challenges in narrowing threshold voltage distributions for reliable data reading and writing, which increases stress on memory cells and prolongs write time due to the need for fine verify operations and higher voltages.

Innovation Solution

A nonvolatile semiconductor memory device that performs a first verify operation and a second verify operation with different charge voltages for the bit lines, allowing for parallel verification of threshold voltages and reducing the shift amount of threshold voltages, thereby shortening the program sequence time and improving read accuracy.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a fine verify operation is performed to narrow the threshold voltage distribution, then the reliability of data reading is improved, but the write time increases

Engineering Contradiction:

Improvereliability of data readingVSAvoidwrite time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The verify operation is segmented into multiple verify levels (first verify level and second verify level), where each level uses different verify voltages and bit line charge voltages to progressively narrow the threshold voltage distribution. This segmentation allows the verify process to be more efficient while achieving the required reliability.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent changes the verify voltage and bit line charge voltage parameters across different verify levels. By adjusting these parameters progressively, the threshold voltage distribution is narrowed efficiently without requiring excessive time, resolving the contradiction between reliability and write time.

Inventive Principle:

Principle #35Parameter changes

2Reliability

If the threshold voltage of each data is increased to increase the margin between threshold voltage distributions, then the margin is improved, but the stress on memory cells increases

Engineering Contradiction:

Improvemargin between threshold voltage distributionsVSAvoidstress on memory cells

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent divides the verify process into multiple levels with progressively adjusted verify voltages and bit line charge voltages. This segmentation allows the margin between threshold voltage distributions to be increased through controlled verification rather than by excessively increasing individual threshold voltages, thereby reducing stress on memory cells.

Inventive Principle:

Principle #1Segmentation

3Manufacturing precision

If higher verify voltages and increased bit line charge voltages are applied to narrow the threshold voltage distribution, then the manufacturing precision is improved, but the stress on memory cells increases

Engineering Contradiction:

Improvethreshold voltage distribution narrownessVSAvoidstress on memory cells

Core Design Contradiction:

Manufacturing precisionVSObject-affected harmful factors

Solution Approach 1:

The patent employs parameter changes across multiple verify levels, where verify voltages and bit line charge voltages are progressively adjusted. This approach achieves narrow threshold voltage distribution (improved manufacturing precision) without applying excessively high voltages simultaneously, thereby reducing stress on memory cells.

Inventive Principle:

Principle #35Parameter changes

4Device complexity

If a single verify operation is performed, then the device complexity is reduced, but the verify time increases

Engineering Contradiction:

Improveverify operation structureVSAvoidverify time

Core Design Contradiction:

Device complexityVSLoss of time

Solution Approach 1:

The verify operation is segmented into multiple verify levels with different verify voltages and bit line charge voltages. Although this increases the structural complexity slightly, it significantly reduces the total verify time by enabling more efficient progressive verification, thus resolving the contradiction between device complexity and verify time.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS9672926B2Apparatus and method of programming and verification for a nonvolatile semiconductor memory device

Publication Date: 2017.06.06 KIOXIA CORP

AI summary

According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control circuit configured to repeat a program operation and a verify operation. The control circuit performs a first verify operation of sensing whether threshold voltages of selected memory cells are greater than or equal to a first threshold voltage, and a second verify operation of sensing whether the threshold voltages of the selected memory cells are greater than or equal to a second threshold voltage (first threshold voltage<second threshold voltage), and the control circuit changes a charge voltage for the bit lines between the first verify operation and the second verify operation.