Memory Device Verify Voltage Timing Adjustment

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Solution Overview

Problem

As integration density of memory devices increases, interference between memory cells and metal lines grows, affecting the reliability of verify operations during program operations in three-dimensionally structured memory blocks.

Innovation Solution

A memory device with a peripheral circuit that adjusts the time point for applying a verify voltage to a selected word line based on the order of program operations, using a control logic circuit to transmit operation codes for adjusting the timing of verify voltage output.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If integration density of memory devices is increased, then storage capacity is improved, but interference between memory cells and metal lines increases

Engineering Contradiction:

Improvestorage capacityVSAvoidinterference between memory cells and metal lines

Core Design Contradiction:

Quantity of substanceVSObject-affected harmful factors

Solution Approach 1:

The patent applies dynamics by making the verify operation timing adjustable rather than fixed. The peripheral circuit changes the time point at which verify voltage is applied based on the program operation order, allowing the system to adapt to interference conditions in densely integrated memory structures.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes the timing parameter of the verify operation. By adjusting when the verify voltage is applied relative to the program operation sequence, the system optimizes performance in high-density configurations where interference is present.

Inventive Principle:

Principle #35Parameter changes

2Reliability

If verify operation timing is adjusted according to program operation order, then reliability of verify operation is improved, but device complexity increases

Engineering Contradiction:

Improvereliability of verify operationVSAvoidcomplexity of peripheral circuit

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The peripheral circuit performs preliminary adjustment of the verify operation timing based on the known program operation order. By pre-configuring the timing according to the operation sequence, the system achieves reliable verify operations without requiring complex real-time adjustments during execution.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS11929126B2Memory device and operating method of the memory device

Publication Date: 2024.03.12 SK HYNIX INC

AI summary

A memory device, and a method of operating the memory device, includes a memory block in which a plurality of cell pages are coupled to each of word lines. The memory device also includes a peripheral circuit configured to adjust a time point at which a verify voltage is applied to a selected word line among the word lines according to an order of performing a program operation during a verify operation of a selected cell page. The memory device further includes a control logic circuit configured to transmit, to the peripheral circuit, an operation code for adjusting a time point at which the verify voltage is output.