3D Memory Device Vertical Bit Line Protrusions
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Solution Overview
Problem
Current semiconductor memory devices face challenges in achieving high integration and reducing manufacturing costs due to limitations in pattern fineness and device reliability, particularly in forming three-dimensional memory cell arrays.
Innovation Solution
A semiconductor memory device with a vertically stacked structure, comprising layer groups with word lines, channel layers, and data storage elements, where the bit line extends vertically and connects memory cell transistors across layers, and a method of fabrication involving sequential stacking of insulating layers, channel layer deposition, and recess formation to enhance integration and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional or planar semiconductor devices are used, then manufacturing process is simpler, but integration is limited by area occupied by unit memory cell
Solution Approach 1:
The patent transitions from two-dimensional planar devices to three-dimensional vertically stacked devices. Multiple memory cell layers are stacked vertically with word lines extending in the first direction and bit lines extending in the second direction, enabling high integration without increasing planar area. This dimensional change allows significant increase in storage capacity per unit area.
2Quantity of substance
If three-dimensional memory cell arrays are formed, then integration is increased, but floating body effects reduce device reliability
Solution Approach 1:
The patent extracts or removes the problematic floating body effect by implementing a specific structure where channel layers are positioned between bit line protrusion portions. This structural arrangement eliminates the floating body effect that normally occurs in three-dimensional memory structures, thereby maintaining device reliability while achieving high integration.
3Ease of manufacture
If channel layers are positioned below word lines in all layers, then fabrication is simplified, but signal transmission efficiency is reduced
Solution Approach 1:
The patent introduces asymmetry in channel layer positioning across different memory cell layers. In first memory cell layers, channel layers are positioned below word lines, while in second memory cell layers, channel layers are positioned above word lines. This alternating asymmetric arrangement optimizes signal transmission efficiency while remaining compatible with fabrication processes.
4Ease of operation
If bit lines extend horizontally, then connection to channel layers is easier, but vertical signal transmission is inefficient
Solution Approach 1:
The patent changes the orientation of bit lines from horizontal to vertical extension. Bit lines extend in the second direction (vertical) and connect to channel layers through protrusion portions that extend in the first direction (horizontal). This three-dimensional arrangement enables both easy connection to channel layers and efficient vertical signal transmission across multiple memory cell layers.
Data Source
AI summary
A semiconductor memory device including a stack structure including layer groups that are vertically stacked on a substrate and including a word line, a channel layer, and a data storage element that is electrically connected to the channel layer; and a vertically extending bit line on one side of the stack structure, wherein the word line of each of the layer groups extends in a first direction parallel to a top surface of the substrate, the layer groups include first and second layer groups that are sequentially stacked, the channel layer is below the word line of the first layer group, the channel layer is above the word line of the second layer group, and the bit line includes a first protrusion portion connected to the channel layer of the first layer group; and a second protrusion portion connected to the channel layer of the second layer group.