3D Memory Via Structure Assembly with Dielectric Core

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Solution Overview

Problem

Current semiconductor technologies face challenges in efficiently forming three-dimensional memory arrays with through-memory-level via structures that allow for the integration of memory stack structures and metal interconnects while maintaining structural integrity and reducing manufacturing costs.

Innovation Solution

A semiconductor structure and method involving an alternating stack of insulating and conductive layers, with memory stack structures extending through the stack, and a via structure assembly that includes a tubular conductive portion, a planar conductive portion, and a dielectric via core, formed using a simultaneous deposition process and anisotropic etching to create a monolithic three-dimensional NAND memory device.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If through-memory-level via structures are formed to integrate memory stack structures and metal interconnects, then device functionality and integration are improved, but manufacturing complexity and cost increase

Engineering Contradiction:

Improveintegration of memory stack structures and metal interconnectsVSAvoidmanufacturing complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent combines the formation of trenches through the alternating stack and via cavities through the dielectric material portion into a single anisotropic etch process. This merging of operations creates both structures simultaneously, reducing the total number of process steps and simplifying manufacturing while maintaining the required three-dimensional architecture for memory stack and interconnect integration

Inventive Principle:

Principle #5Merging (Combining)

2Manufacturing precision

If multiple separate processing steps are used to form trenches and via cavities, then manufacturing precision can be maintained, but processing time and productivity decrease

Engineering Contradiction:

Improvestructural integrityVSAvoidprocessing efficiency

Core Design Contradiction:

Manufacturing precisionVSProductivity

Solution Approach 1:

The patent implements continuous useful action by performing the formation of trenches and via cavities in a single uninterrupted anisotropic etch process. The etch process continuously removes material along vertical paths through both the alternating stack and dielectric material portion without requiring intermediate steps, thereby maintaining precision through consistent process parameters while maximizing productivity through uninterrupted processing

Inventive Principle:

Principle #20Continuity of useful action

3Ease of manufacture

If conventional via formation methods are used, then manufacturing simplicity is maintained, but mechanical stress increases and structural integrity decreases

Engineering Contradiction:

Improvemanufacturing simplicityVSAvoidstructural integrity

Core Design Contradiction:

Ease of manufactureVSStrength

Solution Approach 1:

The patent introduces a dielectric via core as an intermediary structure within the via cavity. This dielectric core serves as a mechanical support element that reduces stress concentration in the via region while maintaining the overall simplicity of the manufacturing process. The dielectric material portion surrounding the via structure assembly also acts as a stress-distributing intermediary that protects the substrate bonding pad area

Inventive Principle:

Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables the cost-effective fabrication of three-dimensional memory arrays with improved structural integrity and reduced processing steps, allowing for efficient integration of memory stack structures and metal interconnects, while also reducing mechanical stress through the use of dielectric via cores.

Implementation Method 1

forming a trench extending through the alternating stack and a via cavity extending through the at least one dielectric material portion using a same anisotropic etch process

Methodology Applied

Scientific EffectAnisotropic etching:

Implementation Method 2

forming a trench fill structure in the trench and a via structure assembly in the via cavity using simultaneous deposition of material portions in the trench and the via cavity

Methodology Applied

Scientific EffectSimultaneous deposition:

Data Source

PatentUS11127655B2Memory die containing through-memory-level via structure and methods for making the same

Publication Date: 2021.09.21 SANDISK TECHNOLOGIES LLC

AI summary

An alternating stack of insulating layers and spacer material layers is formed over a substrate. At least one dielectric material portion is formed over the substrate adjacent to the alternating stack. Memory stack structures are formed through the alternating stack. A trench extending through the alternating stack and a via cavity extending through the at least one dielectric material portion are formed using a same anisotropic etch process. The via cavity is deeper than the trench and the via cavity extends into an upper portion of the substrate. The sacrificial material layers are replaced with electrically conductive layers using the trench as a conduit for an etchant and a reactant. A trench fill structure is formed in the trench, and a via structure assembly is formed in the via cavity using simultaneous deposition of material portions. A bonding pad may be formed on the bottom surface of the via structure assembly.