3D Memory Via Structures Using Dielectric Spacer Plates
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Solution Overview
Problem
Current methods for creating three-dimensional memory devices with through-array contact via structures are costly and time-consuming, as they require complex processing steps and high precision in forming interconnects through alternating stacks of insulating and conductive layers.
Innovation Solution
The development of a three-dimensional memory device with liner-less through-array contact via structures, where a vertically alternating sequence of insulating and dielectric spacer plates is formed between dielectric wall structures, allowing for the direct formation of conductive via structures through the alternating stack without contacting adjacent dielectric walls, using a method that involves forming alternating stacks of insulating and sacrificial material layers, patterning, and isotropic etching to create backside recesses and dielectric spacer plates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If complex processing steps are used to form through-array contact via structures, then manufacturing precision is improved, but device complexity and processing cost increase
Solution Approach 1:
Dielectric spacer plates are formed between the alternating stack layers during the initial fabrication process, before the through-array contact via structures are created. These pre-positioned spacer plates serve as etch stops and alignment references, enabling simpler subsequent via formation processes while maintaining high precision.
Solution Approach 2:
The dielectric spacer plates act as intermediary structures that facilitate the formation of through-array contact via structures. They provide physical references and etch selectivity, allowing the via formation process to proceed with simpler processing steps while achieving the required precision.
2Manufacturing precision
If complex processing steps are used to form through-array contact via structures, then manufacturing precision is improved, but processing time increases
Solution Approach 1:
Dielectric spacer plates are formed between the alternating stack layers during the initial fabrication process, before the through-array contact via structures are created. These pre-positioned spacer plates serve as etch stops and alignment references, enabling simpler subsequent via formation processes while maintaining high precision.
Solution Approach 2:
The dielectric spacer plates act as intermediary structures that facilitate the formation of through-array contact via structures. They provide physical references and etch selectivity, allowing the via formation process to proceed with simpler processing steps and reduced time.
3Reliability
If dielectric wall structures are used to separate adjacent alternating stacks, then reliability is improved, but device complexity increases
Solution Approach 1:
The dielectric spacer plates serve multiple functions: they provide isolation between adjacent alternating stacks (reliability), serve as etch stop layers during via formation, and act as alignment references for subsequent processing steps. This multi-functionality reduces the need for separate dedicated isolation structures, thereby reducing overall device complexity.
Solution Approach 2:
The dielectric spacer plates act as intermediary structures that facilitate the formation of through-array contact via structures. They provide physical references and etch selectivity, allowing the via formation process to proceed with simpler processing steps and reduced time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces processing complexity and cost by enabling efficient formation of interconnects within the memory device, enhancing the integration of memory stack structures while maintaining high precision and reducing processing time.
Implementation Method 1
isotropically etching portions of the sacrificial material layers of the plurality of alternating stacks selective to the insulating layers of the plurality of alternating stacks by introducing an isotropic etchant into the backside trenches
Data Source
AI summary
An alternating layer stack of insulating layers and sacrificial material layers is formed over a semiconductor substrate, and memory stack structures are formed through the vertically-alternating layer stack. A pair of unconnected barrier trenches or a moat trench is formed through the alternating stack concurrently with formation of backside trenches. Backside recesses are formed by isotropically etching the sacrificial material layers selective to the insulating layers while a dielectric liner covers the barrier trenches or the moat trench. A vertically alternating sequence of the insulating plates and the dielectric spacer plates is provided between the pair of barrier trenches or inside the moat trench. Electrically conductive layers are formed in the backside recesses. A first conductive via structure is formed through the vertically alternating sequence concurrently with formation of a second conductive via structure through a dielectric material portion adjacent to the alternating stack.