Memory Contact Via Etching with EPD Layer Depth Control
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Solution Overview
Problem
It is difficult to etch contact via holes to proper depths in different regions of a semiconductor memory device, particularly in the bit line and gate structures, due to challenges in precise control of the etching process.
Innovation Solution
A semiconductor memory device manufacturing method that includes forming a bit line and gate structures, followed by a dielectric layer, and using an etch process diagnostic (EPD) signal layer within a hard mask layer to monitor and control the etching process, with precise timing for main and over etching steps to form via holes, and filling these with conductive materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching process is used to form contact via holes, then the etching can be completed, but the depth control in different regions (bit line area vs. gate area) is imprecise
Solution Approach 1:
The etching process is segmented into multiple distinct steps: main etching step to form via holes through the dielectric layer to expose the bit line metal and gate electrode, and over-etching step to further etch to expose the active area. This segmentation allows precise control of etching depth for different regions by controlling the duration of each step independently.
Solution Approach 2:
The bit line structure and gate structure are formed preliminarily before the etching process, with the bit line mask and gate mask already in place. This preliminary action establishes reference points that guide the subsequent etching process, ensuring that via holes are etched to the correct depths relative to these pre-formed structures.
2Length of stationary object
If etching time is extended to reach deeper structures, then deeper via holes are formed, but the upper layers are over-etched and damaged
Solution Approach 1:
The etching process is divided into a main etching step with a first time period to form via holes to a specific depth, and an over-etching step with a second time period (20%-30% of the first time period) to further etch without damaging upper layers. This temporal segmentation prevents over-etching damage while achieving the required via hole depth.
Solution Approach 2:
The etching process uses periodic action with two distinct time periods: the first time period for main etching to form via holes, and the second time period (20%-30% of the first) for over-etching to expose the active area. This periodic control ensures precise depth achievement without compromising layer integrity.
Data Source
AI summary
A semiconductor memory device manufacturing method includes the following steps. A bit line structure is formed in a memory array area of a substrate. A gate structure is formed in a periphery area of the substrate. A dielectric layer is formed over the bit line structure and the gate structure. A lower hard mask layer is formed over the dielectric layer. An etch process diagnostic signal layer is formed over the lower hard mask layer. An upper hard mask layer is formed over the etch process diagnostic signal layer. A main etching step is performed to form a first via hole towards the bit line structure and a second via hole towards the gate structure until the upper hard mask layer is removed to expose the etch process diagnostic signal layer.