Stacked Memory Bit Line Via Layout for Area-Performance Tuning
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Solution Overview
Problem
Current memory devices with stacked memory cell arrays face challenges in efficiently adjusting both planar area and performance, as the existing designs either reduce planar area at the cost of performance or enhance performance at the expense of increased planar area, limiting flexibility in design optimization.
Innovation Solution
The proposed memory device architecture includes a lower structure with a peripheral circuit and upper structures stacked vertically, featuring a unique bonding pad and via connection scheme that allows for flexible connection of bit lines to either the same or different nodes, enabling adjustment of planar area and performance by selectively connecting bit lines to the peripheral circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If memory cell arrays are stacked to reduce planar area, then area is reduced, but performance adjustment becomes difficult
Solution Approach 1:
The patent implements dynamic configurability by allowing bit lines to be selectively connected to either the same node or different nodes through a configurable connection structure. This enables the memory device to adjust its performance characteristics after fabrication, providing adaptability in a compact stacked architecture where traditional performance tuning would require larger planar area for additional circuitry.
Solution Approach 2:
The invention transitions from planar performance adjustment to vertical dimension utilization. By stacking memory cell arrays vertically and implementing configurable bit line connections in the vertical stacking direction, the patent enables performance adjustment without increasing planar area. The bit lines can be connected to different memory cell arrays at different vertical levels, providing performance tuning capability in the vertical dimension.
2Reliability
If more transistors are added to peripheral circuit for performance enhancement, then performance is improved, but planar area increases
Solution Approach 1:
The patent implements dynamic performance adjustment by configuring bit line connections to different nodes or memory cell arrays based on performance requirements. This eliminates the need for additional transistors in the peripheral circuit, as performance is tuned through the configurable connection architecture rather than through increased circuit complexity.
Solution Approach 2:
The configurable bit line connection structure serves multiple functions: it enables performance adjustment, supports different operating modes, and provides scalability. This multi-functional approach replaces what would traditionally require separate dedicated circuits for each function, thereby avoiding increases in planar area while enhancing performance capabilities.
3Device complexity
If bit lines are connected to the same node to reduce complexity, then device complexity is reduced, but performance is limited
Solution Approach 1:
The patent implements a dynamically configurable connection system where bit lines can be selectively connected to either the same node or different nodes/memory cell arrays. This dynamic configurability allows the system to optimize between complexity and performance based on operational requirements, providing high performance when needed without permanently increasing device complexity.
Solution Approach 2:
The invention segments the connection architecture into configurable units that can be independently configured. Each bit line connection can be independently set to connect to different nodes or memory cell arrays, allowing fine-grained control over performance while maintaining manageable device complexity through modular configuration rather than monolithic complex circuitry.
Data Source
AI summary
A memory device includes a lower structure and a plurality of upper structures stacked on the lower structure. The lower structure includes a peripheral circuit, and an upper bonding pad disposed on a top surface of the lower structure. Each of the plurality of upper structures includes a bit line, a through via, and a lower bonding pad disposed on a bottom surface of the upper structures and connected to the through via. Each of upper structures, other than an uppermost upper structure, further includes an upper bonding pad disposed on a top surface thereof and connected to the through via. The bit line includes a gap separating a first portion of the bit line from a second portion thereof in the horizontal direction, and the through via overlaps the gap of the bit line in a plan view.