Memory Circuit Via Insulation for Leakage-Resistant Cell Stability

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Solution Overview

Problem

Existing memory technologies face challenges in maintaining data retention and stability, particularly in volatile memory cells, where reading can inadvertently alter the stored state, and in non-volatile memory cells, where reading can reverse the polarization state, necessitating immediate rewriting.

Innovation Solution

The use of SiOxCy insulative material in memory circuitry, treated to remove carbon and etched selectively, enhances the formation of memory cells by reducing voids and leakage, improving the integrity of capacitors and transistors, and ensuring stable data storage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional memory cell structures are used, then manufacturing is simpler, but data retention and stability are poor due to voids and leakage

Engineering Contradiction:
Improvedata retention and stabilityVSAvoidcavity filling integrity
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by forming a mandrel structure before depositing the conductive fill material. The mandrel serves as a template that ensures complete cavity filling and prevents void formation. This preliminary structural preparation enables subsequent manufacturing steps to proceed with higher precision and reliability, directly addressing the contradiction between manufacturing simplicity and data retention stability.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The mandrel acts as an intermediary element during the manufacturing process. It is temporarily introduced to facilitate proper material deposition and cavity filling, then removed after serving its purpose. This intermediary structure enables achieving high manufacturing precision without permanently complicating the final device architecture, resolving the contradiction between manufacturing complexity and reliability.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of operation

If reading operations are performed on non-volatile memory cells, then data can be accessed, but the polarization state can reverse requiring immediate rewriting

Engineering Contradiction:
Improvedata accessVSAvoidpolarization state stability
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The patent employs beforehand cushioning by designing the memory cell with enhanced structural support and optimized material layers that cushion and stabilize the polarization state during read operations. The improved cavity filling and reduced leakage create a more robust electrical environment that prevents accidental polarization reversal, allowing data access without compromising stability.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

3Speed

If volatile memory is used, then writing and reading is fast, but data is lost when power is removed requiring constant refreshing

Engineering Contradiction:
Improvewrite and read speedVSAvoiddata retention without power
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent merges characteristics of both volatile and non-volatile memory approaches. By improving the physical structure and material composition of the memory cell, it achieves the fast switching speeds of volatile memory while incorporating structural features that enhance data retention characteristics, creating a hybrid performance profile that addresses both speed and reliability concerns.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method improves the filling of cavities in memory arrays, reducing shorting and leakage, thereby enhancing the stability and reliability of memory cells, ensuring non-volatile data retention and minimizing the need for immediate rewriting.

Implementation Method 1

An uppermost portion of the SiOxCy is treated to remove carbon therefrom

Methodology Applied
Scientific EffectOxidation: Oxidation

Implementation Method 2

the treated uppermost portion of the SiOxCy is etched selectively relative to a lowest portion of the SiOxCy

Methodology Applied
Scientific EffectSelective etching:

Implementation Method 3

Insulative material is formed in the cavity that is circumferentially around the individual conductive via

Methodology Applied
Scientific EffectPhysical containment: Physical Containment

Implementation Method 4

Energy as an electric field may be electrostatically stored within such material

Methodology Applied
Scientific EffectElectrostatic energy storage: Electrostatics

Implementation Method 5

Ferroelectric materials are characterized by having two stable polarized states and thereby can comprise programmable material of a capacitor and/or memory cell. The polarization state of the ferroelectric material can be changed by application of suitable programming voltages and remains after removal of the programming voltage

Methodology Applied
Scientific EffectFerroelectricity:

Data Source

PatentUS20250364015A1Memory Circuitry And Methods Used In Forming Memory Circuitry
Publication Date: 2025.11.27 MICRON TECHNOLOGY INC
  • US20250364015A1 patent drawing
  • US20250364015A1 patent drawing
  • US20250364015A1 patent drawing

AI summary

Memory circuitry comprises transistors individually comprising one and another source/drain regions, a channel region there-between, and a gate operatively proximate the channel region. Conductive vias are individually directly above and electrically coupled to individual of the another source/drain regions and are individually in a cavity that is in insulating material that is laterally over sides of the one source/drain regions of multiple of the transistors. Insulative material is in the cavity circumferentially around the individual conductive via and comprises SiOxCy, where “x” is 0.46 to 1.8 and “y” is 0.01 to 1.1. At least a majority of the insulative material in the cavity is being the SiOxCy. Digitlines are individually directly electrically coupled to a plurality of the conductive vias along a line of a plurality of the transistors. Storage elements are individually electrically coupled to individual of the one source/drain regions. Other embodiments, including method, are disclosed.