Memory Interconnect Layout for Via Isolation and Low Resistance
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Solution Overview
Problem
Current semiconductor memory devices face challenges in improving operational reliability due to limitations in the design of conductive layers and vias, which affect voltage withstand and resistance, leading to potential decoupling and reduced manufacturing yield.
Innovation Solution
The semiconductor memory device incorporates a specific structure with conductive layers and vias where the upper surfaces of the layers overlapping the via are thinner than those not overlapping, increasing the distance between the conductive layers and vias, thereby enhancing voltage withstand and reducing electric resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the conductive layers are made thinner to reduce resistance, then electrical conductivity improves, but voltage withstand capability deteriorates
Solution Approach 1:
The conductive layers have different thicknesses in different regions: thinner in regions overlapping with via plugs to reduce resistance, and thicker in non-overlapping regions to maintain voltage withstand capability. This local variation in thickness optimizes both electrical conductivity and insulation performance in their respective locations.
Solution Approach 2:
The patent introduces a vertical dimension variation in conductive layer thickness to solve the two-dimensional trade-off between resistance and voltage withstand. By controlling thickness in the vertical direction at different horizontal positions, both electrical performance and insulation are optimized simultaneously.
2Reliability
If the via plugs are enlarged to improve connection reliability, then electrical connection improves, but the risk of decoupling and manufacturing defects increases
Solution Approach 1:
The conductive layers are selectively thinned only in regions where via plugs are present, while maintaining adequate thickness elsewhere. This localized thickness adjustment provides optimal electrical connection where needed without compromising overall structural integrity or creating manufacturing defects.
Solution Approach 2:
The patent changes the thickness parameter of conductive layers based on spatial location relative to via plugs. This parameter variation optimizes the balance between connection reliability and manufacturing yield by preventing both decoupling and excessive removal of conductive material.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes a first insulating layer; a first conductive layer provided in the first insulating layer and extending in the first direction; a second conductive layer extending in the first direction and provided adjacent to the first conductive layer in a second direction; and a contact plug coupled to one surface of the first conductive layer in a third direction. Thicknesses in the third direction of portions of the first and second conductive layers that overlap the contact plug in the third direction are smaller than thicknesses in the third direction of portions of the first and second conductive layers that do not overlap the contact plug in the third direction.