3D Memory Via Structure with Projecting Part for Compact Chip Design
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Solution Overview
Problem
Existing semiconductor devices face challenges in reducing chip size and processing complexity due to interference between vias and word lines in three-dimensional memory cell arrays, leading to increased space requirements and risk of over-etching during via formation.
Innovation Solution
A connection structure where the via Z1 contacts the word line while being insulated from lower layer word lines, using a projecting part that exceeds the insulating film to ensure contact without interference, and a method involving specific materials and etching processes to form the contact region, reducing the number of vias needed and minimizing space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If vias are formed to contact word lines in three-dimensional memory cell arrays, then electrical connection is achieved, but interference between vias and word lines occurs leading to increased space requirements and risk of over-etching
Solution Approach 1:
The patent transitions from planar via formation to three-dimensional via formation that extends through multiple word line layers. The via structure is designed to contact multiple word lines at different heights simultaneously, utilizing the vertical dimension to reduce the number of separate via structures needed, thereby reducing overall chip area while maintaining reliable electrical connections.
Solution Approach 2:
The via structure is designed to nest through multiple inter-layer insulating films and contact multiple word lines at different levels. The via acts as a nested structure that passes through insulating layers to establish connections with word lines at various heights, consolidating multiple connection functions into a single via structure.
2Reliability
If vias are formed to contact word lines in three-dimensional memory cell arrays, then electrical connection is achieved, but interference between vias and word lines occurs leading to processing complexity
Solution Approach 1:
Inter-layer insulating films are formed with predetermined thicknesses and material compositions before via formation. These insulating films are designed in advance to provide appropriate etch selectivity and mechanical support, enabling simplified via formation processes that can simultaneously contact multiple word lines without complex masking or alignment steps.
Solution Approach 2:
The patent utilizes variations in insulating film thickness and material composition as controllable parameters to manage via formation. By adjusting these parameters, the etching process can be optimized to contact word lines at different heights selectively, reducing processing complexity while ensuring reliable electrical connections.
3Reliability
If vias are formed to contact word lines in three-dimensional memory cell arrays, then electrical connection is achieved, but risk of over-etching increases during via formation
Solution Approach 1:
Inter-layer insulating films serve as intermediary layers between the via structure and the word lines. These insulating films are specifically designed to provide etch stop functionality, acting as a mediator that prevents the etching process from penetrating too deeply and causing over-etching. The insulating films allow controlled contact with word lines while protecting underlying structures from damage.
Solution Approach 2:
The inter-layer insulating films are formed beforehand to provide a cushioning effect during via etching. These pre-formed insulating layers with appropriate thickness and material properties create a buffer zone that absorbs etching variations and prevents over-etching, ensuring manufacturing precision while maintaining reliable electrical connections.
Data Source
AI summary
A semiconductor device according to an embodiment includes: a stacked body including a plurality of first conductive films stacked via an inter-layer insulating film; a first conductive body contacting the stacked body to extend in a stacking direction; and a plurality of first insulating films in the same layers as the first conductive films and disposed between the first conductive body and the first conductive films, the first conductive body including a projecting part that projects along tops of one of the first insulating films and one of the first conductive films, and a side surface of the projecting part contacting an upper surface of the one of the first conductive films.