Memory Via Protection Layers to Prevent Over-Etch Contact Resistance
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Solution Overview
Problem
During the etching process of forming memory devices, vias in the peripheral region are often over-etched, leading to exposed gaps and high contact resistance or abnormal contact between vias, which affects the performance of resistive memory devices.
Innovation Solution
A method involving the formation of sacrificial layers on the vias, followed by their removal to create recesses, and the embedding of protective layers within these recesses to prevent damage during subsequent etching processes, ensuring proper electrical connection between vias and reducing contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If etching process is used to form vias in peripheral region, then via formation is achieved, but over-etching occurs causing gaps and high contact resistance
Solution Approach 1:
A protective layer is formed in the via before the etching process to prevent over-etching damage. This preliminary protective action ensures that the via walls are not damaged during etching, maintaining via integrity and preventing gap formation that would lead to high contact resistance.
Solution Approach 2:
The protective layer acts as a cushioning barrier that absorbs the harmful effect of over-etching. By placing this protective layer beforehand, the etching process can proceed without causing damage to the via structure, thus preventing the formation of gaps and ensuring reliable electrical contact.
2Reliability
If protective layers are formed in vias, then contact resistance is reduced, but process complexity increases
Solution Approach 1:
The protective layer formation is merged with the existing via formation process flow. The protective layer is deposited conformally during the via formation sequence, combining the protection function with the standard manufacturing process rather than adding a completely separate process step.
Data Source
AI summary
A method for manufacturing a semiconductor device, including the following steps. A plurality of first vias are formed in a first dielectric layer in a memory cell region and a peripheral region. A surface treatment is performed on the plurality of first vias to form a plurality of sacrificial layers. The plurality of sacrificial layers are removed to form a plurality of recesses. A plurality of protective layers are formed in the plurality of recesses. A memory device is formed on the first dielectric layer in the memory cell region. A second dielectric layer is formed on the memory device and on the first dielectric layer. A plurality of second vias is formed in the second dielectric layer in the memory cell region and the peripheral region to electrically connect the memory device in the memory cell region and the first vias in the peripheral region, respectively.