Memory Via Structures for Backside Word Line Delay Reduction
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Solution Overview
Problem
As semiconductor technology scales down, word line (WL) resistance and capacitance increase, leading to degraded memory access speed and design complexity due to narrower polysilicon lines and indirect connections in backside metal lines.
Innovation Solution
Implementing via structures to connect frontside and backside interconnect structures, enabling a backside WL scheme that improves WL delay without significantly impacting device area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If polysilicon lines are narrowed to increase device integration, then more devices can be integrated into the single chip, but word line resistance and capacitance increase leading to degraded memory access speed
Solution Approach 1:
The patent implements a backside global fly word line architecture where the word line is divided into frontside and backside segments. The backside segment is routed on the opposite surface of the substrate, transitioning from a planar two-dimensional layout to a three-dimensional configuration that utilizes vertical stacking. This dimensional change allows the word line to bypass resistance and capacitance limitations of narrow polysilicon lines while maintaining high device integration density.
2Adaptability or versatility
If backside metal lines are used to connect interconnect structures, then routing flexibility is improved, but design complexity increases due to indirect connections
Solution Approach 1:
The word line is segmented into distinct frontside and backside portions, with each segment performing a specific function. The frontside word line segment connects to memory cell gates, while the backside global fly word line segment provides the return path. This segmentation allows each portion to be optimized independently, reducing overall design complexity while maintaining routing flexibility through the backside connection.
Data Source
AI summary
A memory device includes a plurality of first memory cells formed in a first area of a substrate, a plurality of first via structures formed in a second area of the substrate, the second area being disposed next to the first area along a first lateral direction, a first one of a plurality of frontside interconnect structures formed on a first side of the substrate, wherein the first frontside interconnect structure is coupled to gate terminals of access transistors of the plurality of first memory cells, and a first one of a plurality of backside interconnect structures formed on a second side of the substrate vertically opposite to the first side, wherein the first backside interconnect structure is coupled to the first frontside interconnect structure through one or more of the plurality of first via structures.