Unified Memory Visibility Ordering for CPU-GPU Systems
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Solution Overview
Problem
Existing computing systems face challenges in efficiently scheduling and managing the combined use of CPUs and GPUs for unified computing operations, particularly in reordering visibility orders of operations across shared memory, which hampers overall system performance.
Innovation Solution
A method is introduced to reorder the visibility order of operations in a computer arrangement with GPU and CPU threads accessing shared memory, determining the class of each operation and permitting reordering based on these classes to ensure proper visibility in shared memory, thereby enabling unified memory model operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If separate memory systems are used for CPU and GPU, then each processor can have dedicated memory access, but system complexity increases and coordination between processors becomes more difficult
Solution Approach 1:
The patent merges the memory systems of CPU and GPU into a unified shared memory space. This allows both processors to access the same memory without requiring complex inter-memory coordination, thereby reducing system complexity while maintaining high productivity through efficient resource sharing.
2Reliability
If visibility order of operations is maintained strictly, then correctness of memory access is ensured, but scheduling flexibility is reduced and performance is hampered
Solution Approach 1:
The patent introduces dynamic visibility ordering where the memory model can adaptively determine the visibility order of operations based on the class of operations and scheduling context. This allows the system to maintain correctness for critical operations while permitting reordering for performance-optimized operations, thus achieving both reliability and productivity.
3Productivity
If unified memory model is implemented, then resource utilization is optimized, but challenges in scheduling and QoS guarantees between processes increase
Solution Approach 1:
The patent segments memory operations into different classes (e.g., read operations, write operations, atomic operations) with distinct visibility ordering requirements. This segmentation allows the scheduling system to apply different policies to different operation classes, simplifying the overall scheduling complexity while maintaining high resource utilization through unified memory access.
4Productivity
If operation reordering is permitted, then system performance is improved, but ensuring correct visibility of operations across different processors becomes more difficult
Solution Approach 1:
The patent applies local quality by assigning different visibility ordering characteristics to different memory operations based on their class. Critical operations maintain strict visibility ordering to ensure correctness, while non-critical operations allow reordering for performance optimization. This localized differentiation enables both improved performance and maintained reliability.
Data Source
AI summary
Provided is a method of permitting the reordering of a visibility order of operations in a computer arrangement configured for permitting a first processor and a second processor threads to access a shared memory. The method includes receiving in a program order, a first and a second operation in a first thread and permitting the reordering of the visibility order for the operations in the shared memory based on the class of each operation. The visibility order determines the visibility in the shared memory, by a second thread, of stored results from the execution of the first and second operations.