LDPC-TCM Memory Decoding for High-Density Low-SNR Reads

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Solution Overview

Problem

As storage density increases in memory devices, the signal-to-noise ratio (SNR) associated with read operations decreases, necessitating stronger error-correction codes to prevent read errors, particularly in Flash memory where existing algebraic error-correction codes like BCH codes are insufficient.

Innovation Solution

Combining low-density parity-check (LDPC) codes with trellis-coded modulation (TCM) and using a Viterbi algorithm for decoding, which expands the signal set from binary to multilevel data, effectively increasing the signal-to-noise ratio (SNR) without code rate loss.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If storage density is increased in memory devices, then memory capacity is improved, but signal-to-noise ratio decreases leading to increased read errors

Engineering Contradiction:
Improvestorage densityVSAvoidsignal-to-noise ratio
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent combines two error correction approaches: algebraic error correction codes (BCH codes) and trellis-coded modulation (TCM) with soft decision decoding. This hybrid approach merges the strengths of both methods to achieve superior error correction performance at high storage densities where traditional single-method approaches fail due to degraded signal-to-noise ratio

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The error correction system uses a composite structure combining algebraic code components (BCH encoder/decoder) with TCM components (modulator/demodulator with Viterbi algorithm). This composite error correction architecture integrates different error correction mechanisms to handle the increased error rates associated with high-density storage while maintaining data integrity

Inventive Principle:
Principle #40Composite materials

2Ease of manufacture

If traditional algebraic error-correction codes like BCH codes are used, then implementation is simple, but error correction capability is insufficient for high-density storage

Engineering Contradiction:
Improveimplementation simplicityVSAvoiderror correction capability
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent merges traditional algebraic BCH codes with trellis-coded modulation to create a hybrid error correction system. This combination maintains the implementation advantages of algebraic codes while adding the enhanced error correction capability of TCM with soft decision decoding, making it suitable for high-density storage applications

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If trellis-coded modulation is used alone, then signal-to-noise ratio is improved, but code rate loss occurs

Engineering Contradiction:
Improvesignal-to-noise ratioVSAvoidcode rate
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent combines TCM with algebraic BCH codes in a hybrid architecture where the algebraic code component helps maintain code rate efficiency while the TCM component with soft decision decoding provides the necessary signal-to-noise ratio improvement. This merger allows the system to achieve both goals simultaneously

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS8892986B2Apparatuses and methods for combining error coding and modulation schemes
Publication Date: 2014.11.18 MICRON TECHNOLOGY INC
  • US8892986B2 patent drawing
  • US8892986B2 patent drawing
  • US8892986B2 patent drawing

AI summary

Methods and apparatuses for combining error coding and modulation schemes are described herein. One or more methods include encoding data using linear error correcting code, modulating the encoded data, writing the modulated data to memory, and decoding the written data using a Viterbi algorithm and a linear error correcting code decoder.