Memory System Voltage Adaptation for Legacy Compatibility
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Solution Overview
Problem
Memory systems face compatibility issues when transitioning from older to newer power supply voltage standards, as existing solutions either require additional hardware, leading to increased costs, or cause electrical reliability problems due to unduly high voltage application during power setting periods.
Innovation Solution
A memory system that dynamically adjusts power supply voltage from a lower level (e.g., 2.5V) to a higher level (e.g., 3.3V) after a power setting period, using a host device with a PMIC to query the memory device for required voltage information and selectively supply the appropriate voltage without additional hardware modifications, thus maintaining backward compatibility without electrical reliability issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the power supply voltage is lowered to reduce power consumption according to updated standards, then energy efficiency is improved, but compatibility with older memory devices operating under previous standards deteriorates
Solution Approach 1:
The memory system dynamically adjusts the power supply voltage level based on the detected standard version of the connected memory device. During initialization, the host device queries the memory device to determine which standard it complies with, then selectively applies either the lower voltage (for updated standards) or higher voltage (for older standards). This dynamic adaptation allows the system to optimize power consumption when possible while maintaining broad compatibility across different device generations.
2Adaptability or versatility
If additional hardware is added to maintain compatibility with older memory devices, then backward compatibility is improved, but device complexity and cost increase
Solution Approach 1:
The memory device itself provides the information needed to determine the appropriate voltage level through its response to standard query commands during initialization. The device controller stores and transmits device information including the required power supply voltage level, allowing the host device to automatically configure itself without requiring external hardware modifications or additional compatibility circuits.
3Adaptability or versatility
If high voltage is applied during the power setting period to ensure compatibility, then compatibility with older devices is maintained, but electrical reliability and safety deteriorate due to potential overvoltage damage
Solution Approach 1:
The host device performs a preliminary voltage level determination during the initialization phase by querying the memory device's standard compliance information before applying the actual operating voltage. This preliminary action allows the system to pre-configure the appropriate voltage level, ensuring that the correct voltage is applied from the start rather than risking overvoltage damage by defaulting to high voltage during the power setting period.
Solution Approach 2:
The memory device provides feedback about its standard compliance and voltage requirements through device information stored in the device controller. The host device uses this feedback to adjust its voltage output accordingly, creating a closed-loop control system that prevents overvoltage application while maintaining compatibility with both older and updated memory device standards.
Data Source
AI summary
A memory system includes a storage device and a host device. The storage device includes a memory device and a device controller. The device controller is configured to store device information. The device information includes a level of a power supply voltage required for the memory device. The host device includes a host controller and a power management integrated circuit (PMIC). The host device is configured to send a query command to receive the device information from the device controller during a power setting period. The PMIC is configured to supply a first level of power supply voltage to the memory device during the power setting period and, after the power setting period, selectively supply one of the first level of power supply voltage and a second level of power supply voltage to the memory device. The first level of power supply voltage is lower than the second level of power supply voltage.


