Variable Resistance Memory Voltage Control

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Solution Overview

Problem

Conventional semiconductor memory devices, such as ReRAMs, face reliability issues due to decreased simultaneously selected bits during data write or erase operations, leading to increased voltage on memory cells and potential destruction or miswriting, which degrades reliability.

Innovation Solution

A method for controlling semiconductor memory devices involves determining the select bit number, setting and adjusting the write voltage based on the number of selected memory cells, and performing verify reads to ensure all cells meet a predetermined value, thereby preventing extra loads on memory cells and improving reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If data write or erase control is performed on a mass of plurality of bits, then productivity is improved, but reliability deteriorates due to increased voltage on memory cells

Engineering Contradiction:
Improvedata write/erase operation efficiencyVSAvoidmemory cell reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies dynamics by making the write voltage adjustable rather than fixed. The control circuit dynamically sets the write voltage based on the number of simultaneously selected bits, reducing the voltage when fewer bits are selected to prevent extra loads on memory cells while maintaining high productivity through mass bit operations

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent implements feedback by having the control circuit monitor the number of simultaneously selected bits and adjust the write voltage accordingly. This feedback mechanism ensures that the voltage is optimized for the actual number of memory cells being operated on, preventing reliability issues while maintaining efficient mass operations

Inventive Principle:
Principle #23Feedback

2Device complexity

If the number of simultaneously selected bits decreases, then device complexity is reduced, but voltage on memory cells increases causing potential destruction or miswriting

Engineering Contradiction:
Improvecontrol circuit complexityVSAvoidvoltage-induced damage to memory cells
Core Design Contradiction:
Device complexityVSObject-affected harmful factors

Solution Approach 1:

The patent applies parameter changes by modifying the write voltage parameter based on the number of simultaneously selected bits. When the number of selected bits decreases, the control circuit reduces the write voltage to prevent extra loads on memory cells, thereby eliminating voltage-induced damage while maintaining simple control logic

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS8488367B2Semiconductor memory device and method for controlling the same
Publication Date: 2013.07.16 KIOXIA CORP
  • US8488367B2 patent drawing
  • US8488367B2 patent drawing
  • US8488367B2 patent drawing

AI summary

According to one embodiment, a method for controlling a semiconductor device comprises determining a select bit number for a group of memory cells each includes a variable-resistance element, setting a first voltage corresponding to the select bit number, applying the set first voltage to the memory cell group, and performing verify read on the memory cell group to which the first voltage has been applied and determining whether or not the memory cell group passes the verify read. If the memory cell group is determined not to pass the verify read, the number of bits corresponding to passed memory cells is subtracted from the select bit number, and the first voltage corresponding to the decreased select bit number is set again.