Memory Threshold Voltage Bin Calibration at Power Up
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Solution Overview
Problem
Existing memory sub-systems face challenges in accurately and efficiently recalibrating threshold voltage offset bins at memory device power up, leading to potential increased bit error rates and inefficient data management.
Innovation Solution
The proposed solution involves identifying a subset of voltage offset bins that produce acceptable data state metrics and selecting the bin with the smallest threshold voltage offset for association with block families, thereby improving calibration efficiency and accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If full calibration of all voltage offset bins is performed at memory device power up, then calibration accuracy is improved, but calibration time and processing overhead increase significantly
Solution Approach 1:
The patent segments the calibration process by dividing all voltage offset bins into a subset of candidate bins that are likely to contain the optimal threshold voltage offset. Instead of calibrating all bins, the system performs calibration only on this segmented subset, thereby reducing calibration time while maintaining accuracy. The segmentation is based on preliminary analysis of memory block characteristics and historical calibration data.
Solution Approach 2:
The patent applies partial action by performing calibration on only the necessary subset of voltage offset bins rather than all bins. The system identifies and calibrates only those bins that are relevant to the current memory device state and block family characteristics, avoiding unnecessary calibration operations on bins that would not improve performance.
2Measurement precision
If comprehensive calibration across all bins is performed, then bin assignment accuracy is improved, but device productivity and operational efficiency decrease
Solution Approach 1:
The calibration process is segmented to focus only on the relevant subset of voltage offset bins. The system divides the full bin range into candidate bins based on device characteristics and calibration requirements, performing detailed calibration only on this segmented portion while skipping unnecessary bins, thus maintaining accuracy without sacrificing productivity.
Solution Approach 2:
The system performs preliminary analysis to identify the candidate subset of voltage offset bins before executing the full calibration process. This preliminary action involves assessing memory block characteristics, historical performance data, and device state to pre-determine which bins require calibration, thereby avoiding time-consuming calibration of irrelevant bins.
3Reliability
If traditional calibration methods are used, then thorough calibration is achieved, but the number of folding operations and processing complexity increase
Solution Approach 1:
The patent extracts and removes unnecessary calibration operations from the traditional calibration process. By identifying and excluding voltage offset bins that do not require calibration, the system eliminates redundant processing steps and folding operations, thereby reducing processing complexity while maintaining calibration thoroughness for the relevant bins.
Solution Approach 2:
The system performs partial calibration action by focusing computational resources only on the necessary subset of bins. This approach avoids excessive processing on all bins, reducing the number of folding operations and overall processing complexity while still achieving thorough calibration where needed.
Data Source
AI summary
An example method of threshold voltage offset calibration at memory device power up comprises: identifying a set of memory pages that have been programmed within a time window; determining, for each voltage offset bin of a plurality of voltage offset bins, a corresponding value of a data state metric produced by a memory access operation with respect to a memory page of the set of memory pages; identifying a subset of the plurality of voltage offset bins, such that memory access operations performed using the corresponding voltage offsets produced respective values of the data state metric that satisfy a predefined quality criterion; selecting, among the subset of the plurality of voltage offset bins, a voltage offset bin that is associated with the lowest voltage offset; and associating the set of memory pages with the selected voltage offset bin.