Memory Subsystem Voltage Bin Selection Optimization
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Solution Overview
Problem
Existing memory sub-systems fail to adequately address temporal voltage shift in memory cells, leading to increased bit error rates due to slow charge loss, and often employ inefficient strategies that result in high error rates.
Innovation Solution
Implementing a memory sub-system that assigns each block a voltage bin based on its age, using binary search and segmented binary search algorithms to optimize voltage bin selection, thereby minimizing performance overhead and improving accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If voltage bin selection is performed for all blocks, then accuracy is improved, but performance overhead increases
Solution Approach 1:
The patent segments blocks into different categories based on their operational characteristics (e.g., blocks that have undergone wear leveling vs. those that have not). This segmentation allows the system to apply different voltage bin selection strategies to different block types, achieving high accuracy for critical blocks while using more efficient (lower overhead) methods for less critical blocks.
Solution Approach 2:
The patent applies local quality by tailoring voltage bin selection methods to specific block characteristics. Instead of using a uniform approach for all blocks, the system adjusts the selection methodology based on local block properties such as age, wear level, and operational history, optimizing both accuracy and performance overhead for each local context.
2Measurement precision
If complex voltage bin selection algorithms are used, then accuracy is improved, but device complexity increases
Solution Approach 1:
The patent divides the voltage bin selection process into separate stages: first segmenting blocks into categories based on simple criteria (wear level, age), then applying different algorithmic complexities to each segment. This allows complex algorithms to be used only where necessary (for blocks requiring high precision) while using simpler algorithms for other blocks, thereby reducing overall device complexity.
Solution Approach 2:
The patent applies partial action by using simplified voltage bin selection methods for blocks where maximum accuracy is not critical, and reserving complex algorithms only for blocks where high precision is essential. This partial application of complex algorithms reduces the overall computational burden and device complexity while maintaining sufficient accuracy for most operations.
Data Source
AI summary
A processing device of a memory sub-system is configured to sort a plurality of blocks of the memory device; identify, based on scanning of a first block at a first location of the plurality of sorted block, a first voltage bin associated with the first block; identify, based on scanning of a second block at a second location of the plurality of sorted blocks, a second voltage bin associated with the second block; and responsive to determining that the first voltage bin matches the second voltage bin, assign the first voltage bin to each block that is located between the first location of the plurality of sorted blocks and the second location of the plurality of sorted blocks.