Memory Voltage Bin Calibration via Transition Boundary Detection
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Solution Overview
Problem
Existing memory sub-systems face inefficiencies due to temporal voltage shift caused by slow charge loss in memory cells, leading to increased bit error rates and latency in read operations, as current strategies fail to adequately address this issue.
Innovation Solution
The implementation of a memory sub-system that employs read threshold voltage bins and adjusts threshold voltage offsets based on the time after programming and temperature, identifying blocks approaching a transition boundary to proactively reassign them to subsequent bins, thereby minimizing performance and bandwidth penalties during calibration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If voltage bin calibration is performed by scanning all blocks, then accurate threshold voltage offset determination is achieved, but performance and bandwidth overhead increase significantly
Solution Approach 1:
The patent segments the block population into two groups: blocks approaching transition boundaries and blocks not approaching transition boundaries. Only the former group is scanned for calibration, representing a small subset of total blocks. This segmentation allows accurate calibration to be performed on a manageable subset, resolving the contradiction between calibration accuracy and performance overhead.
Solution Approach 2:
The patent performs preliminary identification of blocks approaching transition boundaries before calibration. By pre-selecting only those blocks that require calibration (those near transition boundaries), the system avoids scanning all blocks, thus maintaining calibration accuracy while minimizing performance and bandwidth overhead.
2Reliability
If threshold voltage offset is adjusted to compensate for temporal voltage shift, then bit error rate decreases, but read operation latency increases due to calibration overhead
Solution Approach 1:
The patent applies partial calibration action by calibrating only the subset of blocks approaching transition boundaries rather than all blocks. This partial action is sufficient to maintain low bit error rates for the critical blocks while avoiding the time penalty of calibrating unnecessary blocks, thus resolving the contradiction between reliability and latency.
3Productivity
If voltage bins are used to manage temporal voltage shift, then read efficiency is improved, but complexity increases due to bin management and transition tracking
Solution Approach 1:
The patent implements self-service by having the system automatically track which blocks are approaching transition boundaries and initiate calibration only when needed. This automated self-monitoring and self-calibration approach improves read efficiency while managing complexity through intelligent automation rather than manual intervention.
Data Source
AI summary
A processing device of a memory sub-system is configured to identify a plurality of blocks assigned to a first voltage bin of a plurality of voltage bins of a memory device; identify a subset of the plurality of blocks having a time after program (TAP) within a predetermined threshold period of time from a second TAP associated with a transition boundary between the first voltage bin and a subsequent voltage bin of the plurality of voltage bins; determine a threshold voltage offset associated with the subset of blocks; and associate the threshold voltage offset with the subsequent voltage bin.