Memory Voltage Generation with Active-Block Clock Scaling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor memories, particularly flash memories, consume excessive current in peripheral circuits due to fixed clock frequencies set for the maximum number of activated memory blocks, even when fewer blocks are active.
Innovation Solution
A memory device with a voltage generator and control logic that adjusts the clock frequency based on the number of active blocks, allowing independent memory operations and reducing current consumption in peripheral circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the clock frequency is set considering the maximum number of memory blocks activated simultaneously, then the memory device can handle maximum parallel operations, but excessive current is consumed when fewer blocks are activated
Solution Approach 1:
The clock frequency is made dynamic rather than fixed. The pump circuit changes the clock frequency according to the number of active blocks activated during independent memory operations. When fewer blocks are active, the clock frequency is reduced accordingly, preventing excessive current consumption while maintaining the ability to handle maximum parallel operations when all blocks are active.
Solution Approach 2:
The clock frequency parameter is changed based on the number of active blocks. The system monitors how many memory blocks are currently active and adjusts the clock frequency parameter accordingly. This parameter adaptation allows the system to optimize between productivity and energy consumption by matching the clock frequency to the actual operational demand.
2Device complexity
If a fixed clock frequency is used for generating operating voltage, then the circuit design is simplified, but current consumption increases when not all memory blocks are active
Solution Approach 1:
The system transitions from a static fixed clock frequency to a dynamic adjustable clock frequency. The pump circuit is designed to respond to the number of active blocks and adjust the clock frequency accordingly. This dynamic approach increases energy efficiency without significantly complicating the circuit design, as the adjustment mechanism is integrated into the existing voltage generation architecture.
3Productivity
If the clock frequency is optimized for maximum active blocks, then parallel processing performance is maximized, but power efficiency deteriorates when fewer blocks are active
Solution Approach 1:
The clock frequency parameter is dynamically changed based on the actual number of active blocks. When all blocks are active, the clock frequency is set to the optimal value for maximum parallel processing performance. When fewer blocks are active, the clock frequency is reduced proportionally, eliminating unnecessary energy consumption while maintaining adequate processing performance for the current workload.
Solution Approach 2:
The system implements feedback by monitoring the number of active blocks and using this information to adjust the clock frequency. This feedback mechanism ensures that the clock frequency always matches the current operational requirements, preventing energy waste when fewer blocks are active while maintaining optimal performance when all blocks are utilized.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A memory device (1100) is disclosed including a memory cell array (1100), a voltage generator (1150), and a control logic (1160). The memory cell array (1100) has a plurality of active blocks (Active BLK1 to Active BLKn), each active block including a plurality of memory cells (MC1 to MCm) operating at the same clock frequency. The voltage generator (1150) provides an operating voltage to the plurality of memory cells (MC1 to MCm). The control logic (1160) controls an independent memory operation for each active block. The voltage generator (1150) includes a pump circuit (2000) which changes a clock frequency for generating the operating voltage according to a number of active blocks activated during the independent memory operation.