3D Memory Device Voltage Control for Program Disturbance

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Solution Overview

Problem

Three-dimensionally structured memory devices face challenges in improving the reliability of memory operations, particularly in verify and read operations, due to limitations in voltage control and discharge sequences that affect the accuracy and efficiency of data storage and retrieval.

Innovation Solution

A memory device design that includes a memory block with word lines arranged between select lines, peripheral circuits for supplying and discharging voltages, and control logic to manage these voltages, ensuring that selected and unselected word lines and select lines have equal potentials during verify and read operations, and sequential discharge of word lines to prevent channel voltage reduction.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If verify voltage is applied to selected word line during verify operation, then memory cell verification accuracy is improved, but channel voltage reduction and program disturbance may occur

Engineering Contradiction:
Improveverification accuracyVSAvoidprogram stability
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The patent applies equipotentiality by maintaining the same voltage level (e.g., ground potential) across selected and unselected word lines during the verify operation. After applying verify voltage to the selected word line, both selected and unselected word lines are discharged to the same potential before the verify operation begins, and unselected word lines are discharged first during the discharge phase. This equalizes the electrical environment and prevents voltage differences that could cause program disturbance or channel voltage reduction, thereby resolving the contradiction between verification accuracy and program stability.

Inventive Principle:
Principle #12Equipotentiality

2Quantity of substance

If three-dimensional memory structure is used to increase integration density, then storage capacity is improved, but voltage control complexity and reliability challenges increase

Engineering Contradiction:
Improveintegration densityVSAvoidoperation reliability
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent applies segmentation by dividing the word lines into selected and unselected groups with different discharge sequences. In the three-dimensional memory structure, this segmentation approach is applied to the vertical word lines by controlling their discharge timing - unselected word lines are discharged first to ground potential, then the selected word line is discharged. This segmented control strategy manages the voltage distribution complexity inherent in 3D structures, preventing interference between vertically stacked memory cells and improving operation reliability while maintaining high integration density.

Inventive Principle:
Principle #1Segmentation

3Reliability

If sequential discharge of word lines is implemented, then program disturbance is prevented, but operation time increases

Engineering Contradiction:
Improveprogram stabilityVSAvoidverify operation time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies periodic action through the structured discharge sequence of word lines. The discharge operation is divided into distinct phases: first, unselected word lines are discharged to ground potential in a periodic manner; then, the selected word line is discharged in a subsequent phase. This periodic, phased discharge approach ensures that voltage transitions occur in a controlled sequence, preventing program disturbance while minimizing the total discharge time. The method balances reliability requirements with time efficiency by optimizing the timing and sequencing of voltage transitions.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS10438647B2Memory device and operating method thereof
Publication Date: 2019.10.08 SK HYNIX INC
  • US10438647B2 patent drawing
  • US10438647B2 patent drawing
  • US10438647B2 patent drawing

AI summary

A memory device includes a memory block coupled to a plurality of word lines arranged in parallel with each other between a first select line and a second select line, peripheral circuits supplying a verify voltage and a pass voltage to the first select line, the second select line, and the word lines, selectively discharging the first select line, the second select line and the word lines, and verifying memory cells coupled to a selected word line of the word lines, and a control logic controlling the peripheral circuits so that potentials of the selected word line, unselected word lines and the first and second select lines are the same as each other after verifying the memory cells and the first and second select lines are discharged after discharging the selected and unselected word lines, and an operating method thereof.