Semiconductor Memory Device Voltage Control for Threshold Stability
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Solution Overview
Problem
Current semiconductor memory devices face challenges in efficiently writing data due to voltage fluctuations and erroneous writing, particularly in maintaining threshold voltage stability over time, which affects data retention and read operations.
Innovation Solution
The semiconductor memory device employs a specific voltage management strategy during write operations, where the k-th first word line receives a first voltage higher than the reference voltage, and the k-th second word line receives a second voltage lower than the reference voltage, with controlled voltages applied to select gate lines, word lines, and bit lines to stabilize the threshold voltage of memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional voltage management is used during write operations, then write speed is maintained, but threshold voltage stability deteriorates due to voltage fluctuations
Solution Approach 1:
The patent dynamically adjusts the voltage levels applied to word lines during write operations based on the specific operation being performed. Different voltage levels (Vch0, Vch1, Vch2) are applied to different word lines (k-th first word line, k-th second word line, (k-1)-th first word line, (k+1)-th second word line) to precisely control the threshold voltage of memory cells during program and verify operations, thereby maintaining stability while enabling efficient write operations.
Solution Approach 2:
The patent changes the voltage parameters applied to word lines during different phases of the write operation. By applying higher voltages during program operations and lower voltages during verify operations, the system maintains threshold voltage stability while preventing erroneous writing. The voltage levels are specifically adjusted to create appropriate potential differences between selected and unselected word lines.
2Reliability
If higher voltages are applied to stabilize threshold voltage, then data retention is improved, but erroneous writing increases due to voltage fluctuations
Solution Approach 1:
The patent applies different voltage levels to different word lines based on their specific role in the operation. The k-th first word line receives a first voltage level, the k-th second word line receives a second voltage level, the (k-1)-th first word line receives a third voltage level, and the (k+1)-th second word line receives a fourth voltage level. This localized voltage control ensures that only the intended memory cells are affected, preventing erroneous writing to adjacent cells while maintaining stable threshold voltage in the target cells.
Solution Approach 2:
The patent applies preliminary voltage control to prevent erroneous writing before it can occur. By establishing appropriate voltage levels on all relevant word lines before the write operation begins, the system creates a protective voltage landscape that prevents charge leakage or unintended programming in adjacent memory cells, thereby preventing erroneous writing while maintaining data retention in the target cells.
Data Source
AI summary
A semiconductor memory device includes a first semiconductor pillar having i first memory cells on a first side and i second memory cells on a second side, a second semiconductor pillar having i third memory cells on a third side and i fourth memory cells on a fourth side, i first word lines (i is an integer of 4 or more) connected to the i first memory cells and the i third memory cells, i second word lines connected to the i second memory cells and the i fourth memory, and a driver. In writing data to the k-th (k is smaller than i and greater than 1) first memory cell, the driver supplies the k-th first word line with a first voltage larger than a reference voltage, and supplies the k-th second word line with a second voltage smaller than the reference voltage.