Memory Read Voltage Adjustment for Defect and Tail Bit Separation
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Solution Overview
Problem
Existing memory technologies face challenges in distinguishing defect bits and tail bits, leading to increased movement times of the word line reference voltage, which slows down reading speed and reduces the reading margin, especially in SLC and MLC memory systems.
Innovation Solution
A moving algorithm that learns and adjusts the word line reference voltage by comparing error bit numbers in each read, allowing for the distinction between defect bits and tail bits, and uses Error Checking and Correcting (ECC) to cover defect bits, thereby reducing unnecessary voltage movements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the word line reference voltage is moved multiple times to cover defect bits and tail bits, then the reading accuracy is improved, but the reading speed deteriorates
Solution Approach 1:
The patent segments the bit distributions into three distinct categories: main bits distribution, tail bits distribution, and defect bits distribution. By identifying and separately handling each segment with appropriate voltage levels, the system avoids unnecessary voltage movements while maintaining reading accuracy for all bit types.
Solution Approach 2:
The patent performs preliminary classification of bits into main bits, tail bits, and defect bits before the actual reading operation. This preliminary action allows the system to pre-determine the appropriate word line reference voltage levels, eliminating the need for multiple iterative voltage movements during reading and thus improving reading speed.
2Reliability
If the word line reference voltage is moved multiple times to cover both defect bits and tail bits, then the reading coverage is improved, but the reading margin is reduced
Solution Approach 1:
The patent applies different word line reference voltage levels tailored to specific bit distributions: main bits use one voltage level, tail bits use another, and defect bits use a third. This local quality approach ensures each bit type is read with the optimal voltage, maintaining large reading margins while achieving complete coverage.
Solution Approach 2:
The patent changes the word line reference voltage parameter based on the identified bit distribution type. By adjusting the voltage parameter to match the specific distribution (main, tail, or defect bits), the system achieves both wide coverage and large reading margins without the need for repeated voltage movements.
3Reliability
If the word line reference voltage is moved multiple times across different pages in the same word line, then the reading completeness is improved, but the time consumption increases
Solution Approach 1:
The patent establishes a universal voltage movement strategy that can be applied across all pages within the same word line. By determining the appropriate voltage level once for the word line and applying it universally to all pages, the system achieves complete reading coverage without repeating voltage movements for each page, thus reducing time consumption.
4Reliability
If the moving algorithm is used to adjust the word line reference voltage, then the error correction capability is improved, but the device complexity increases
Solution Approach 1:
The patent employs a feedback mechanism where the reading results are compared with original data to determine whether voltage movement is needed. This feedback-based approach provides error correction capability by systematically adjusting voltage levels based on actual reading performance, while keeping the algorithm relatively simple through clear decision rules.
Data Source
AI summary
An operation method for a memory device having a plurality of memory cells includes: reading the plurality of memory cells by a first word line voltage to get a first number of a first logic state; reading the plurality of memory cells by a second word line voltage to get a second number of the first logic state, the second word line voltage different from the first word line voltage; and using the second word line voltage as a target word line voltage if the first number of the first logic state is equal to the second number of the first logic state.