Nonvolatile Memory Voltage Control Using Degeneration Feedback
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Solution Overview
Problem
Existing nonvolatile memory devices face inefficiencies in data transfer during command and address transmission due to the degradation of memory cells, leading to increased stress and reduced performance and lifetime.
Innovation Solution
A nonvolatile memory device employing a Separate Command Address (SCA) protocol that transfers degeneration information via distinct pins, allowing the storage controller to adjust program and erase voltages based on measured execution times, thereby reducing stress on memory cells and improving performance and lifetime.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is transferred over the same I/O pins used for commands and addresses, then the interface structure is simple, but data transfer efficiency is degraded because data cannot be transferred while commands and addresses are being transferred
Solution Approach 1:
The patent segments the I/O interface into separate channels: one for commands and addresses, and another for data transfer. This allows simultaneous operation of different signal types without interference, resolving the contradiction between interface simplicity and data transfer efficiency.
2Speed
If high voltage is applied to memory cells during program and erase operations, then write and erase speeds are improved, but stress on memory cells increases leading to reduced lifetime
Solution Approach 1:
The patent implements dynamic voltage adjustment based on the degeneration level of memory cells. The controller measures execution times of program and erase operations, determines the degeneration level, and adjusts subsequent operation voltages accordingly. This allows the system to maintain high speeds when cells are healthy while reducing voltage stress as cells degrade, resolving the contradiction between speed and reliability.
Solution Approach 2:
The system incorporates feedback mechanisms where the controller continuously monitors program and erase execution times, determines memory cell degeneration levels, and adjusts operation parameters accordingly. This closed-loop control enables optimal balancing of speed and reliability by adapting voltage levels to the actual state of memory cells.
3Productivity
If the same I/O pins are used for both command/address and data transfer, then the number of pins is reduced, but the I/O interface cannot efficiently transfer data during command and address transmission
Solution Approach 1:
The patent divides the I/O interface into functionally separate pin groups: command/address pins and data pins. This segmentation enables parallel operation where data can be transferred simultaneously with command and address transmission, dramatically improving I/O interface efficiency while accepting the trade-off of increased pin count.
Data Source
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AI summary
A storage device is provided. The storage device includes a nonvolatile memory device configured to receive a command and an address for a write operation or an erase operation via command-address pins, transmit and receive write data or read data via data pins, and generate degeneration information by measuring at least one of a program execution time to perform the write operation and an erase execution time to perform the erase operation; and a storage controller configured to receive the degeneration information from the nonvolatile memory device, and control the nonvolatile memory device to adjust at least one of a program voltage of the write operation and an erase voltage of the erase operation based on the degeneration information.