Memory Voltage Controller for Dynamic Power Optimization
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Solution Overview
Problem
In mobile systems, reducing power consumption is crucial to extend battery life, but existing technologies do not effectively manage power usage by peripherals and processors, leading to inefficient energy management.
Innovation Solution
A memory voltage controller adjusts the operating voltage of system memory based on whether a processor or peripheral is accessing it, using a voltage controller that monitors access requests and adjusts voltage levels to optimize power consumption by providing higher voltage for processor accesses and lower voltage for peripheral accesses, and further adjusts voltage based on data transfer rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the memory operates at a high voltage level to satisfy processor performance requirements, then the processor can access memory at high speed, but the system power consumption increases
Solution Approach 1:
The memory voltage controller dynamically adjusts the memory operating voltage based on real-time detection of bus master identity. When a processor is detected as the bus master, the controller raises the voltage to a higher level to enable fast access. When a peripheral is detected, the controller lowers the voltage to reduce power consumption. This dynamic voltage adjustment resolves the contradiction by making memory speed adaptive rather than static.
Solution Approach 2:
The invention changes the electrical parameter (voltage level) of the memory based on the type of access request. The voltage controller switches between at least two different voltage levels corresponding to different bus masters. This parameter change allows the system to optimize between speed and power consumption by selecting appropriate voltage levels for different operational scenarios.
2Use of energy by moving object
If the memory voltage is lowered to reduce power consumption during peripheral accesses, then battery life is extended, but the data transfer rate decreases
Solution Approach 1:
The invention applies different voltage quality levels to different access scenarios. High voltage quality is provided when processors access memory, ensuring high data transfer rates. Low voltage quality is provided when peripherals access memory, reducing power consumption. The voltage controller locally adapts the voltage quality based on the specific access request, resolving the contradiction between power consumption and transfer rate.
Solution Approach 2:
The voltage controller changes the voltage parameter based on the detected bus master type. For processor accesses, the voltage is maintained at a higher level to ensure adequate transfer rates. For peripheral accesses, the voltage is reduced to lower power consumption. This conditional parameter change optimizes the trade-off between power and performance.
3Reliability
If the system uses a single high voltage level for all memory accesses, then all bus masters can operate at optimal performance, but power consumption increases unnecessarily during peripheral accesses
Solution Approach 1:
The voltage controller dynamically adapts the memory voltage based on the identity of the bus master. The system transitions from a static high-voltage approach to a dynamic voltage adjustment approach. The controller detects whether the bus master is a processor or peripheral and adjusts the voltage accordingly, maintaining performance consistency for processors while reducing power for peripherals.
Solution Approach 2:
The voltage controller periodically monitors the bus master identity and adjusts the voltage level in response to changing access patterns. This periodic detection and adjustment ensures that the memory operates at the appropriate voltage level for each access type, resolving the contradiction between consistent performance and power efficiency.
Data Source
AI summary
A system and method saves power in a system memory of a processing system. A peripheral, a processor, an arbiter and a system memory are coupled to a system communication bus for communicating via the system communication bus. In one form a voltage controller is coupled to the system memory for varying the operating voltage of the system memory based upon whether the data processor or the peripheral is accessing the system memory. In another form a storage buffer is coupled to the memory for receiving and storing data from the memory. The buffer provides at least one signal that is used for either determining a rate at which the storage buffer is being emptied of data or a measure of fullness of the storage buffer. In one form the voltage controller varies the operating voltage of the memory based upon either the rate at which the storage buffer is being emptied of data or the measure of fullness.