Memory Device Voltage Fall Control Circuit

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Solution Overview

Problem

Memory devices utilizing resistance change memory elements face challenges in appropriate fall/rise control of applied voltages, which affects the setting of low and high resistance states.

Innovation Solution

The memory device incorporates a resistance change memory element, a selector element, an operational amplifier, and a charge/discharge circuit with a capacitor, where the potential of the memory cell is set higher than the discharge circuit and capacitor, allowing for controlled voltage fall and rise, enabling precise control of the resistance state transitions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If resistance change memory element is used to achieve low and high resistance states, then memory functionality is enabled, but appropriate fall/rise control of applied voltage is insufficient

Engineering Contradiction:
Improveresistance state setting accuracyVSAvoidvoltage control precision
Core Design Contradiction:
ReliabilityVSEase of operation

Solution Approach 1:

The patent introduces a bit line potential control circuit as an intermediary component between the voltage source and the resistance change memory element. This control circuit actively manages the bit line potential during write operations, enabling precise control of the voltage applied to the memory element. The intermediary circuit includes transistors and capacitors that work together to generate controlled voltage transitions, solving the problem of insufficient voltage fall/rise control while maintaining reliable resistance state setting.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If simple memory cell structure is used, then device complexity is reduced, but write operation efficiency is insufficient

Engineering Contradiction:
Improvewrite operation efficiencyVSAvoidcircuit structure complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements preliminary action by pre-charging the bit line to a specific potential level before the actual write operation. The bit line potential control circuit prepares the voltage conditions in advance, ensuring that when the write signal is applied, the voltage transitions across the resistance change memory element are optimal. This preliminary preparation of voltage conditions enables efficient write operations while keeping the additional circuitry minimal and integrated into the existing memory cell structure.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration allows for appropriate control of the voltage applied to the resistance change memory element, ensuring accurate setting of low and high resistance states, thereby improving the write operation efficiency.

Implementation Method 1

a resistance change memory element in which a low resistance state or a high resistance state can be set according to a falling speed of a voltage to be applied across both terminals

Methodology Applied
Scientific EffectVoltage-dependent resistance change: Electrical Resistance

Implementation Method 2

an operational amplifier including a non-inverting input terminal connected to the bit line, an inverting input terminal, and an output terminal

Methodology Applied
Scientific EffectOperational amplification: Magnetic Amplifier

Implementation Method 3

a charge/discharge circuit which includes a capacitor, a charge circuit section charging the capacitor, and a discharge circuit section discharging the capacitor

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentUS10923189B2Memory device
Publication Date: 2021.02.16 KIOXIA CORP
  • US10923189B2 patent drawing
  • US10923189B2 patent drawing
  • US10923189B2 patent drawing

AI summary

According to one embodiment, a memory device includes a memory cell including a resistance change memory element and a selector element, a word line, a bit line connected to one end of the memory cell, an operational amplifier including a non-inverting input connected to the bit line, an output circuit including a first terminal connected to an output of the operational amplifier, a second terminal connected to the bit line, and a charge/discharge circuit including a capacitor, a charge circuit and a discharge circuit, each including one end connected to an inverting input of the operational amplifier. At the time of falling of a write voltage for the memory cell, a potential of the other end of the memory cell is set higher than a potential of the other end of the discharge circuit.