Memory Device Voltage Generation Circuit for Power Optimization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current memory devices face challenges in efficiently managing power consumption and operation modes, particularly when operating multiple planes in non-interleaved manners, which can lead to increased current consumption.
Innovation Solution
A memory device with a voltage generation circuit comprising a master pump component and sub-pump components that can switch between interleaved and non-interleaved operations, allowing for optimized voltage distribution across multiple planes, reducing current consumption during non-interleaved operations by disabling sub-pump amplifiers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If sub-pump components are activated for each plane during non-interleaved operations, then voltage generation capability is improved, but current consumption increases
Solution Approach 1:
The voltage generation circuit is divided into a master pump component and multiple sub-pump components, where the master pump serves all planes and sub-pumps serve specific planes. During non-interleaved operations, only the master pump is activated, while sub-pump amplifiers are disabled, allowing selective activation of voltage generation components based on operational mode.
Solution Approach 2:
The system dynamically switches between interleaved and non-interleaved operation modes, adjusting the activation state of sub-pump amplifiers accordingly. In non-interleaved mode, sub-pump amplifiers are disabled to reduce current consumption, while in interleaved mode they are activated to provide dedicated voltage generation for each plane.
2Use of energy by moving object
If sub-pump amplifiers are disabled during non-interleaved operations, then current consumption is reduced, but voltage generation flexibility decreases
Solution Approach 1:
The master pump component is designed to serve multiple planes universally, providing voltage generation for any selected plane during non-interleaved operations. This universal design eliminates the need for dedicated sub-pump amplifiers for each plane when operating in non-interleaved mode, reducing component activation while maintaining functionality.
Solution Approach 2:
The system changes operational parameters by switching between interleaved and non-interleaved modes, which controls the activation state of sub-pump amplifiers. This parameter change allows the system to adapt voltage generation flexibility according to the operational mode, maintaining sufficient flexibility when needed while reducing power consumption when operating in a simpler mode.
3Productivity
If dedicated sub-pump components are provided for each plane, then voltage distribution efficiency is improved, but device complexity increases
Solution Approach 1:
The master pump component combines the voltage generation function for all planes, eliminating the need for separate dedicated voltage generation circuits for each plane. By merging these functions into a single master pump that can be selectively activated, the system reduces device complexity while maintaining the ability to provide efficient voltage distribution when needed through selective activation in interleaved mode.
Data Source
AI summary
A memory device may include: a memory cell array including a plurality of planes; and a voltage generation circuit including a master pump component and at least one or more sub-pump components that respectively correspond to the planes. During an interleaved operation, the master pump component may generate a first output voltage in response to a first pump clock, and the sub-pump components may generate second output voltages in response to second pump clocks. The master pump component and the sub-pump components may respectively provide the first output voltage and the second output voltages to the corresponding planes. During a non-interleaved operation, the master pump component and the sub-pump components may generate the first output voltage in response to the first pump clock and provide the first output voltage to a selected plane of the plurality of planes.