Semiconductor Memory Voltage Generator Program Verify Control

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Solution Overview

Problem

Semiconductor memory devices face program disturb issues due to channel potential levels dropping to negative voltages during program verify operations, leading to inefficiencies and potential data loss.

Innovation Solution

Applying a set voltage to the common source line or bit lines during program verify operations to maintain channel potential levels, preventing them from dropping to negative voltages and thus reducing program disturb phenomena.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a program verify operation is performed without applying set voltage to the common source line, then the operation speed is faster, but the channel potential drops to negative voltage level causing program disturb

Engineering Contradiction:
Improvedata integrityVSAvoidprogram verify speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent applies set voltage to the common source line before the channel potential can drop to negative levels during program verify operation. This preliminary action prevents the harmful negative voltage condition from occurring in the first place, thereby maintaining data integrity without requiring corrective measures after the problem arises.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent applies a counteracting voltage (set voltage) to the common source line that opposes and prevents the channel potential from dropping to negative levels. This preliminary anti-action neutralizes the harmful effect before it can cause program disturb, resolving the contradiction between maintaining reliability and preserving operation speed.

Inventive Principle:
Principle #9Preliminary anti-action

2Reliability

If set voltage is applied to the common source line during program verify, then program disturb is reduced, but current consumption increases

Engineering Contradiction:
Improveprogram operation reliabilityVSAvoidcurrent consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent applies set voltage specifically to the common source line only during the program verify operation when needed, rather than continuously or to all lines. This localized application of voltage provides the necessary protection against program disturb while minimizing overall current consumption by limiting the scope and duration of the voltage application.

Inventive Principle:
Principle #3Local quality

3Device complexity

If channel potential is allowed to drop to negative voltage level, then the program verify operation is simpler, but program disturb occurs leading to data loss

Engineering Contradiction:
Improveoperation control complexityVSAvoiddata loss
Core Design Contradiction:
Device complexityVSLoss of information

Solution Approach 1:

The patent implements a preliminary voltage control mechanism that applies set voltage to the common source line before channel potential can drop to harmful negative levels. This adds a control step but prevents data loss by ensuring the channel potential remains within safe boundaries throughout the program verify operation.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10515711B2Semiconductor memory device and operating method thereof for controlling operating voltages
Publication Date: 2019.12.24 SK HYNIX INC
  • US10515711B2 patent drawing
  • US10515711B2 patent drawing
  • US10515711B2 patent drawing

AI summary

A semiconductor memory device includes a memory cell array including a plurality of memory cells coupled between a common source line and a bit line, and a voltage generator applying operating voltages to word lines coupled to the memory cells or discharging potential levels of the word lines, wherein during a program verify operation, the voltage generator applies a program verify voltage and a pass voltage as the operating voltages to the word lines, and subsequently applies a set voltage to the common source line during a period in which the memory cells are turned on.