3D Stacked Memory Voltage Layering
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in optimizing programming voltages for memory cells stacked in a three-dimensional manner, leading to inefficiencies in write operations due to varying characteristics across layers, which affects operational performance.
Innovation Solution
A semiconductor memory device configuration where first and second memory cells are stacked above a semiconductor substrate, with third and fourth memory cells stacked above these, and word lines connected to their gates, allowing a row decoder to apply distinct programming voltages based on layer-dependent characteristics during write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single programming voltage is applied to all memory cells during write operations, then the device structure remains simple, but the write operation efficiency deteriorates due to varying characteristics across stacked layers
Solution Approach 1:
The patent divides the memory cell array into multiple stacked layers (first and second memory cells stacked above each other). The row decoder is configured to apply different programming voltages to different layers during write operations, segmenting the voltage application by layer to account for varying characteristics across the three-dimensional structure
Solution Approach 2:
The patent applies different programming voltages to different layers of memory cells based on their specific characteristics. The row decoder provides localized voltage optimization by applying a first programming voltage to the first memory cell layer and a second programming voltage to the second memory cell layer, ensuring each layer receives the appropriate voltage for its specific operational requirements
2Reliability
If different programming voltages are applied to different stacked layers, then the operational performance improves, but the control circuit complexity increases
Solution Approach 1:
The row decoder is segmented to handle different voltage applications for different layers. The decoder includes separate control paths that can independently apply first programming voltages to first memory cells and second programming voltages to second memory cells, allowing optimized voltage control for each layer while maintaining reliable operation
Solution Approach 2:
The patent changes the voltage parameter applied to different layers of memory cells during write operations. The row decoder is configured to apply different programming voltages (first programming voltage vs. second programming voltage) to different stacked layers, optimizing the electrical parameters for each layer's specific characteristics and improving overall operational reliability
Data Source
AI summary
A semiconductor memory device includes first to fourth memory cells that are stacked above a semiconductor substrate, first to fourth word lines that are connected to gates of the first to fourth memory cells, respectively, and a row decoder that applies voltages to the first to fourth word lines. The row decoder applies a first programming voltage to the first word line during a write operation performed on the first memory cell, applies the first programming voltage to the second word line during a write operation performed on the second memory cell, applies a second programming voltage to the third word line during a write operation performed on the third memory cell, and applies the second programming voltage to the fourth word line during a write operation performed on the fourth memory cell. The second programming voltage is higher than the first programming voltage.