Semiconductor Memory Device Voltage Limiting for Program Disturbance
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Solution Overview
Problem
Current NAND-type flash memory devices face challenges in ensuring reliable data writing, particularly in the upper layer region where program disturbance can lead to unintended data changes due to varying voltage applications across word lines, affecting the reliability of data storage.
Innovation Solution
The semiconductor memory device employs different upper limit voltage values for word lines in the lower and upper layer regions during write operations, with specific voltage settings for non-selected word lines to prevent excessive voltage application and minimize program disturbance, thereby enhancing data writing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single upper limit voltage value is applied to all word lines during write operations, then the device structure remains simple, but program disturbance occurs in the upper layer region leading to unintended data changes
Solution Approach 1:
The patent segments the word lines into two distinct groups: lower layer word lines (first group) and upper layer word lines (second group). Each group is assigned a different upper limit voltage value during write operations. This segmentation allows tailored voltage control for each region, preventing program disturbance in the upper layer while maintaining effective writing in the lower layer, thus resolving the contradiction between reliability and complexity.
Solution Approach 2:
The patent applies local quality by assigning different voltage characteristics to different spatial regions of the memory device. Specifically, upper layer word lines receive a first upper limit voltage value that prevents excessive voltage application and program disturbance, while lower layer word lines receive a second upper limit voltage value that ensures effective data writing. This localized voltage control optimizes performance for each region's specific requirements.
2Reliability
If higher voltage is applied to word lines in the upper layer region, then data writing effectiveness improves, but program disturbance increases causing unintended data changes
Solution Approach 1:
The patent changes the voltage parameter specifically for upper layer word lines by imposing a first upper limit voltage value that is more restrictive than the second upper limit voltage value applied to lower layer word lines. This parameter change directly addresses the program disturbance issue in the upper layer region by preventing excessive voltage application that would cause unintended data changes, while still allowing effective writing operations through controlled voltage levels.
Data Source
AI summary
A semiconductor memory device includes a first memory cell transistor, a second memory cell transistor, and a third memory cell transistor that are connected in series. A word line is coupled to a gate of the third memory cell transistor. A controller is configured to set a first upper limit value for voltages applied to the word line during writing of data to the first memory cell transistor and a second upper limit value for voltages applied to the word line during writing of data to the second memory cell transistor. The second upper limit value is different from the first upper limit value.