Memory Device Mode Selection via External Voltage Detection
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Solution Overview
Problem
The production efficiency of semiconductor memory devices is hindered by the need to manufacture diverse devices according to various communication standards, leading to reduced efficiency and increased costs due to the requirement for multiple manufacturing processes.
Innovation Solution
A memory device that selects an operation mode based on an external voltage signal, allowing it to communicate with a memory controller via an interface corresponding to a chosen standard, such as LPDDR4 or LPDDR4X, using a mode selector and calibrating circuit to adjust voltage levels and configure internal circuit blocks accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If memory devices are manufactured according to various communication standards (LPDDR4, LPDDR4X, etc.), then the memory devices can support diverse interface requirements, but the production efficiency decreases and manufacturing complexity increases
Solution Approach 1:
The memory device is designed with multi-functionality to support multiple interface standards (LPDDR4, LPDDR4X, and future standards) through a single device structure. The mode selector and calibrating circuit enable the device to adapt to different voltage levels and interface requirements, eliminating the need for separate manufacturing lines for each standard and thereby improving production efficiency while maintaining versatility
Solution Approach 2:
The memory device employs dynamic configuration capabilities where the mode selector dynamically determines the operation mode based on externally provided voltage signals. This dynamic adaptability allows the same hardware to function across multiple standards without requiring physical reconfiguration or separate manufacturing processes, resolving the contradiction between versatility and production efficiency
2Manufacturing precision
If separate manufacturing processes are used for different standards, then each standard can be optimized specifically, but the device complexity and manufacturing cost increase
Solution Approach 1:
The patent incorporates preliminary configuration capabilities within the memory device itself through the mode selector and calibrating circuit. These components are pre-designed to handle multiple standards, allowing the device to self-configure its operation mode based on voltage detection rather than requiring external manufacturing differentiation. This preliminary built-in adaptability reduces manufacturing process complexity while maintaining standard-specific optimization
3Productivity
If a unified manufacturing process is used for all standards, then production efficiency improves, but the ability to optimize for specific standards decreases
Solution Approach 1:
The patent utilizes parameter changes in voltage levels as the key differentiator between standards. The mode selector detects voltage level parameters and automatically configures the memory device accordingly. This approach allows unified manufacturing while maintaining standard-specific optimization, as the same hardware can be manufactured once and then dynamically adjusted to different standards through voltage parameter detection and configuration
Data Source
AI summary
A memory device determines an operation mode based on an external voltage. The memory device includes a cell array including a plurality of memory cells; and a mode selector that detects a level of at least one voltage signal externally provided and selects any one of a plurality of operation modes corresponding to a plurality of standards according to a result of detecting the level of the at least one voltage signal. The memory device further includes a mode controller that, in response to a mode selecting signal from the mode selector, outputs setting information for setting the memory device to communicate with a memory controller via an interface according to a selected standard from among the plurality of standards; and a calibrating circuit that generates a control code for controlling circuit blocks in the memory device according to the setting information.