Semiconductor Memory Voltage Generation Parameter Reduction
Solution Overview
Problem
Conventional NAND flash EEPROMs require a large number of parameters for generating verify and read voltages, leading to an increase in the number of EEPROM cells and registers, which occupies a significant area, making it necessary to reduce the number of parameters for generating voltages corresponding to threshold levels.
Innovation Solution
A semiconductor memory device comprising a memory cell, a storage section for parameter data, an arithmetic circuit to calculate voltage data, and a voltage generating circuit that generates voltages based on the calculated data, where the arithmetic circuit accumulates parameter data to reduce the number of parameters needed for voltage generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a large number of parameters are used for generating verify and read voltages, then the accuracy of voltage generation is improved, but the number of EEPROM cells and registers increases, occupying significant area
Solution Approach 1:
The patent segments the parameter storage into two parts: a small number of base parameters stored in EEPROM cells and registers, and additional parameters generated on-chip through arithmetic operations. This segmentation reduces the area occupied by storage elements while maintaining the total number of parameters needed for accurate voltage generation across multiple threshold levels
Solution Approach 2:
The patent replaces the physical storage of all parameters in EEPROM cells and registers with an arithmetic circuit that generates additional parameters through calculations. This substitution reduces the mechanical/storage overhead by using computational logic instead of physical storage elements for all parameters
2Measurement precision
If the number of trimming data items increases to improve voltage accuracy, then the accuracy of output voltage is improved, but the number of EEPROM cells and registers increases
Solution Approach 1:
The patent performs preliminary storage of only essential base parameters in EEPROM cells and registers during manufacturing. The remaining parameters are generated on-chip through arithmetic operations using these base parameters, reducing the preliminary storage requirement while ensuring accurate voltage generation through calculated parameters
Solution Approach 2:
The patent changes the state of parameter storage from completely physical (all parameters in EEPROM) to a hybrid approach where base parameters are physical and derived parameters are computational. This parameter change in storage methodology reduces the quantity of physical storage elements while maintaining the total parameter count for accuracy
Data Source
AI summary
A memory cell MC stores a plurality of bits of data using threshold levels 1, 2, . . . , n (n is a natural number). A storage section stores a plurality of items of parameter data for generating the threshold levels. An arithmetic circuit generates voltage data for generating voltages corresponding to the threshold levels by accumulating the parameter data read from the storage section. A voltage generating circuit generates a voltage on the basis of the voltage data generated by the arithmetic circuit. The arithmetic circuit, when reading data from the memory cell at threshold level k (k<=n), generates the voltage data by accumulating parameter data at the threshold levels i to k (i<=k).