Semiconductor Memory Device Voltage Adjustment for Write Speed Uniformity
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in ensuring uniform write speed across memory cells with varying semiconductor pillar diameters, leading to variations in threshold voltage distribution and potential program disturbance.
Innovation Solution
The semiconductor memory device employs a voltage adjustment scheme where different voltages are applied to bit lines connected to semiconductor pillars of varying diameters, ensuring consistent write speed by using specific voltage values for pillars of different groups based on their diameters, and incorporating a correction write operation to address variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are three-dimensionally arranged with varying semiconductor pillar diameters, then storage capacity increases, but write speed uniformity deteriorates
Solution Approach 1:
The patent applies different voltage values to bit lines connected to semiconductor pillars of different diameter groups. Specifically, first voltage values are applied to bit lines connected to pillars with first diameter, and second voltage values are applied to bit lines connected to pillars with second diameter. This local differentiation of voltage parameters compensates for the varying pillar diameters, ensuring uniform write speed across all memory cells while maintaining three-dimensional arrangement for high storage capacity.
2Manufacturing precision
If different voltages are applied to bit lines based on pillar diameter, then write speed uniformity improves, but device complexity increases
Solution Approach 1:
The patent segments the bit lines into multiple groups based on the diameter of connected semiconductor pillars. Each group is assigned a specific voltage value from a predefined set. This segmentation approach allows systematic management of voltage applications, where the controller identifies the pillar diameter group and applies the corresponding voltage, thereby achieving uniform write speed without requiring complex individualized control for each pillar.
3Manufacturing precision
If voltage adjustment scheme is implemented, then threshold voltage distribution varies less, but operation time increases
Solution Approach 1:
The patent implements a correction write operation that is performed in advance or in conjunction with the main write operation. This correction write applies appropriate voltage adjustments to bit lines based on semiconductor pillar diameter groups before or during the primary write process. By performing this voltage correction preliminarily, the system ensures proper threshold voltage distribution is established upfront, preventing subsequent variations and reducing the need for repeated write operations, thereby actually saving overall operation time.
Data Source
AI summary
A semiconductor memory device includes first and second plugs formed on a semiconductor substrate, a word line between the first and second plugs and above the semiconductor substrate, a first semiconductor pillar extending above the semiconductor substrate through the word line, a second semiconductor pillar extending above the semiconductor substrate through the word line, a first bit line electrically connected to the first semiconductor pillar, and a second bit line electrically connected to the second semiconductor pillar. When writing same data in a first memory cell, which is electrically connected to the first bit line, and a second memory cell, which is electrically connected to the second bit line, a first voltage is applied to the first bit line and a second voltage that is different from the first voltage is applied to the second bit line.