Semiconductor Memory Device Voltage Pulse Control
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Solution Overview
Problem
Semiconductor memory devices face challenges in maintaining data integrity and reliability due to charge redistribution phenomena and power consumption issues, particularly when transitioning between ready and busy states.
Innovation Solution
A semiconductor memory device with a memory cell array and connecting circuits, including pass transistors and an address decoder, applies voltage pulses to global and block word lines based on the operation state to manage charge redistribution and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If voltage is continuously applied to word lines to maintain ready state, then data reliability is improved, but power consumption increases
Solution Approach 1:
The patent applies periodic voltage pulses to word lines instead of continuous voltage application. The control logic generates first voltage pulses for global word lines and second voltage pulses for block word lines at specific periods, maintaining data reliability while reducing average power consumption during ready state transitions.
Solution Approach 2:
The patent applies voltage pulses in advance before state transitions occur. By pre-charging word lines and applying voltage pulses before the memory device transitions from ready to busy state, the system ensures data reliability is maintained without requiring continuous power application.
2Reliability
If voltage pulses are applied to suppress charge redistribution, then data integrity is improved, but power consumption increases
Solution Approach 1:
The patent uses periodic voltage pulses applied only when needed for state transitions rather than continuous application. The control logic monitors operation states and triggers voltage pulses only during ready-to-busy or busy-to-ready transitions, suppressing charge redistribution phenomena while minimizing energy loss.
3Productivity
If fast state transitions are implemented, then productivity is improved, but charge redistribution effects worsen
Solution Approach 1:
The patent applies voltage pulses to word lines in advance before the actual state transition occurs. This pre-charging action prepares the memory cells for rapid transition while maintaining control over charge redistribution, enabling fast state changes without compromising data integrity.
Solution Approach 2:
The control logic implements periodic voltage pulsing synchronized with state transitions. By applying voltage pulses at precise intervals corresponding to ready and busy state changes, the system achieves fast transitions while controlling charge redistribution effects through timed application.
Data Source
AI summary
A semiconductor memory device includes a memory cell array including a plurality of memory cells, connecting circuits including pass transistors coupled between global word lines and the plurality of memory cells, an address decoder coupled to block word lines coupled to gates of the pass transistors and the global word lines, and a control logic controlling the address decoder and applying a voltage pulse to the global word lines and the block word lines according to an operation state of the semiconductor memory device.