Nonvolatile Memory Programming Voltage Ramping

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Solution Overview

Problem

Nonvolatile memory devices face issues with 'program disturb' faults due to unintended programming of non-selected memory cells and reduced programming ability at smaller transistor sizes, leading to increased chip area and longer programming intervals.

Innovation Solution

A method involving a nonvolatile memory device with a memory array, bit line decoder, word line decoder, first and second high voltage generators, where a ramping voltage signal with multiple levels is applied in programming operations to minimize voltage drops on bit lines and prevent unintended programming, using a first word line programming signal with more voltage levels than a second signal, ensuring efficient programming.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If a program voltage is applied to a selected word line to program selected memory cells, then the selected memory cells are programmed successfully, but non-selected memory cells of the selected word line are also programmed unintentionally

Engineering Contradiction:

Improveprogramming precisionVSAvoidprogram disturb fault

Core Design Contradiction:

Manufacturing precisionVSObject-generated harmful factors

Solution Approach 1:

The programming operation is divided into multiple programming slots with different voltage levels. The word line programming signal transitions through multiple voltage stages (e.g., first voltage level for selected cells, second voltage level for non-selected cells) within the same programming operation, allowing selective programming without disturbing non-selected cells.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The word line programming signal is made dynamic by transitioning through multiple voltage levels during the programming operation. The voltage level changes from a first level to a second level across different programming slots, enabling adaptive voltage application that prevents program disturb while ensuring successful programming of selected cells.

Inventive Principle:

Principle #15Dynamics

2Quantity of substance

If the transistor size is reduced to increase memory capacity, then the memory device capacity increases, but the resistance of the bit line increases reducing programming ability

Engineering Contradiction:

Improvememory capacityVSAvoidprogramming ability

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The voltage levels applied to the word line are changed according to the programming slot. By adjusting the word line voltage dynamically through multiple levels, the patent compensates for the increased bit line resistance caused by smaller transistor sizes, ensuring sufficient programming voltage reaches the selected memory cells even when located at the tail end of the bit line.

Inventive Principle:

Principle #35Parameter changes

3Reliability

If a charge pump is used to increase the programming voltage to overcome bit line resistance, then the programming ability improves, but the chip area increases and program disturb fault cannot be avoided

Engineering Contradiction:

Improveprogramming abilityVSAvoidchip area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The word line programming signal serves multiple functions: it programs selected memory cells, prevents program disturb in non-selected cells, and compensates for bit line resistance effects. By making the signal multi-functional through multiple voltage levels, the patent eliminates the need for additional charge pump circuits, reducing chip area while maintaining programming ability.

Inventive Principle:

Principle #6Universality (Multi-functionality)

4Object-generated harmful factors

If multiple ramping times of programming voltage are used to avoid program disturb, then the program disturb fault is avoided, but the programming interval becomes longer

Engineering Contradiction:

Improveprogram disturb faultVSAvoidprogramming interval

Core Design Contradiction:

Object-generated harmful factorsVSLoss of time

Solution Approach 1:

The programming operation continues continuously across multiple programming slots without interruption. The word line programming signal transitions through multiple voltage levels within a single programming operation, maintaining continuous useful action while preventing program disturb. This eliminates the need for multiple separate programming operations, reducing the total programming interval.

Inventive Principle:

Principle #20Continuity of useful action

Data Source

PatentUS9378822B2Method for programming selected memory cells in nonvolatile memory device and nonvolatile memory device thereof

Publication Date: 2016.06.28 ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC

AI summary

A method for programming memory cells of a selected word line has steps of: providing a first word line programming signal being at plurality of voltage levels in different programming slots of a current programming operation to the memory cells of the selected word line, wherein the first word line programming signal is a ramping voltage signal; and providing a second line programming signal being at plurality of voltage levels in different programming slots of a next programming operation to the memory cells of the selected word line, wherein the second word line programming signal is another one ramping voltage signal; wherein the highest voltage levels of the first and second word line programming signals are identical to each other, and a number of the voltage levels of the first word line programming signal is larger than that of the second word line programming signal.