Nonvolatile Memory Voltage Region Segmentation
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Solution Overview
Problem
The complexity of power rail arrangements and increased power consumption in semiconductor memory devices, such as DRAM, due to the need for multiple voltage levels and circuits to manage these voltages, complicates design and increases chip size and energy use.
Innovation Solution
A memory device design that separates power management into two voltage regions: a data path region receiving either high or low power voltage based on operating mode, and a control signal path region continuously receiving high power voltage, with a switch unit controlling the power rail connections to optimize voltage usage and reduce unnecessary circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple voltage levels are used to improve operating performance characteristics, then the desired frequency and operation performance are improved, but the complexity of power rail arrangements and the number of circuits increase
Solution Approach 1:
The patent divides the memory device into two distinct voltage regions: a first voltage region for high-performance operations and a second voltage region for low-power operations. Each region has its own dedicated power rails and voltage generation circuits, allowing independent voltage management without interfering with the other region. This segmentation eliminates the need for complex power rail arrangements that would otherwise be required to distribute multiple voltage levels throughout the entire device.
Solution Approach 2:
The patent applies different voltage characteristics to different spatial regions of the memory device. The first voltage region receives higher voltage levels optimized for fast operations, while the second voltage region receives lower voltage levels optimized for power efficiency. This local differentiation allows each region to operate at optimal performance characteristics without requiring the entire device to support multiple voltage levels through complex routing.
2Productivity
If multiple voltage levels and circuits are used to improve operation performance, then the desired frequency is improved, but power consumption increases
Solution Approach 1:
By segmenting the memory device into separate voltage regions with dedicated power rails, the patent enables independent power management. The second voltage region can operate at lower voltage levels when high performance is not required, reducing overall power consumption without affecting the performance of the first voltage region. This eliminates the need to supply high voltage to the entire device just to achieve high frequency in specific operations.
Solution Approach 2:
The patent implements dynamic voltage control where the voltage supplied to each region can be independently adjusted based on operational requirements. The voltage generation circuits can dynamically switch between different voltage levels and configurations, allowing the device to optimize power consumption by supplying high voltage only to the first voltage region during high-performance operations, while maintaining lower voltage in the second voltage region during normal operations.
3Adaptability or versatility
If more circuits and components are added to manage voltage regions, then voltage control capability is improved, but chip size increases
Solution Approach 1:
The patent divides the chip into separate voltage regions with dedicated power rails and voltage generation circuits for each region. This segmentation allows compact arrangement of voltage management components within each region, eliminating the need for extensive inter-region routing and reducing overall chip area. Each region's voltage management is localized, reducing the space required for power distribution networks and associated control circuits.
Solution Approach 2:
The patent combines multiple functions into integrated voltage generation circuits that can serve both voltage regions. The power rails are configured to distribute voltage efficiently across regions, and the voltage generation logic is merged to control both regions coordinate. This integration reduces the number of discrete components needed and minimizes the space required for voltage management infrastructure.
Data Source
AI summary
A memory device having a plurality of voltage regions and a method of operating the same are provided. The memory device includes a memory cell array, a data path region including data processing blocks transmitting read/write data from/to the memory cell array during read/write operations, and a control signal path region including control blocks controlling the data processing blocks during the read/write operations. The data path region selectively receives a first high power voltage or a first low power voltage in accordance with an operating mode of the memory device. The control signal path region receives the first high power voltage regardless of the operating mode.