Semiconductor Memory Device Voltage Drop Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor memory devices with resistive change elements experience a significant voltage drop when accessing multiple bits, leading to a decrease in operation margin and complexity in address assignment due to the large current requirements.
Innovation Solution
The semiconductor memory device architecture includes a control circuit that strategically selects and connects resistive change elements across multiple word lines and bit lines, dividing them into groups to reduce voltage drop and simplify address assignment by accessing PCM elements on opposite sides of word lines, thereby minimizing the impact of current flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple bits are accessed simultaneously in a stacked semiconductor memory device, then the data access capability is improved, but a large voltage drop occurs leading to decreased operation margin
Solution Approach 1:
The bit lines are divided into multiple segments (first bit line and second bit line) that are electrically connected in parallel between the same word lines. This segmentation distributes the current flow across multiple paths, reducing the voltage drop on each individual bit line segment while maintaining the ability to access multiple bits simultaneously.
Solution Approach 2:
The patent introduces an additional spatial dimension by stacking multiple memory layers vertically and connecting corresponding bit lines across layers through via holes. This three-dimensional arrangement allows current to flow through multiple parallel paths in the vertical dimension, effectively reducing the overall voltage drop when accessing multiple bits.
2Productivity
If multiple bits are accessed simultaneously, then the data access capability is improved, but the address assignment becomes complex
Solution Approach 1:
The bit lines are segmented into first and second bit lines that can be independently controlled by the control circuit. This segmentation allows the control circuit to selectively activate specific bit line segments based on the access pattern, simplifying the address assignment logic compared to managing a single long bit line for multi-bit access.
Solution Approach 2:
The control circuit dynamically selects and activates only the necessary bit line segments based on the specific access requirements. This dynamic control approach simplifies address assignment by enabling the system to adapt the active bit line configuration to the access pattern, rather than requiring all bit lines to be managed simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the voltage drop and maintains operation margin while simplifying the address assignment process, allowing for efficient simultaneous access to multiple bits without complicating the address selection.
Implementation Method 1
a phase-change memory element having a storage layer containing a phase-change material
Data Source
AI summary
A semiconductor memory device of an embodiment includes: a first wiring disposed at a first level and extending in a first direction; a second and third wirings disposed at a second level and extending in the first direction; a plurality of fourth wirings disposed at a third level and extending in a third direction; a plurality of first resistive change elements disposed in intersection regions of the first and fourth wirings; a plurality of second resistive change elements disposed in intersection regions between the second wiring and the third wiring and the fourth wirings; a first driving circuit electrically connected to the first wiring, a second driving circuit electrically connected to the second wiring, and a third driving circuit electrically connected to the third wiring; and a control circuit that controls the first driving circuit, the second driving circuit, and the third driving circuit, and also the fourth wirings.