Semiconductor Memory Voltage Control Segmentation
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Solution Overview
Problem
Current semiconductor memory devices, particularly NAND-type flash memory, face challenges in efficiently managing voltage distributions and operations across multiple word lines and select gate lines during write, read, and erase operations, leading to inefficiencies and potential data loss.
Innovation Solution
The semiconductor memory device incorporates a complex circuit configuration with multiple drivers and selectors that allow for precise control of voltages across word lines and select gate lines through a system of high-voltage n-channel MOS transistors and level shifters, enabling simultaneous operations across multiple planes and blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a simple voltage control circuit is used, then device complexity is reduced, but operational precision and data integrity deteriorate due to inability to precisely control voltages across multiple word lines and select gate lines
Solution Approach 1:
The voltage control circuit is segmented into multiple independent drivers (first driver, second driver, third driver) that can independently control different groups of word lines and select gate lines. This segmentation allows precise voltage control for each segment while maintaining overall system manageability through modular architecture.
Solution Approach 2:
Level shifters are introduced as intermediary components between the drivers and the word lines/select gate lines. These level shifters act as mediators that precisely adjust voltage levels, ensuring accurate voltage control across multiple memory blocks without requiring direct complex control circuitry at each memory cell.
2Productivity
If multiple drivers and selectors are used for precise voltage control, then operational efficiency and data integrity improve, but device complexity increases
Solution Approach 1:
The drivers and selectors are designed with multi-functionality to perform multiple operations (write, read, erase) across different memory blocks using the same circuit architecture. This universality allows the complex circuit to handle diverse operations efficiently without requiring separate dedicated circuits for each function, thereby improving operational efficiency while managing complexity through design consolidation.
Solution Approach 2:
The patent extends voltage control to multiple dimensions by simultaneously controlling voltages across multiple word lines and select gate lines in different memory blocks. This multi-dimensional control enables parallel operations (simultaneous write, read, and erase operations across different blocks), significantly improving productivity by utilizing the third dimension of spatial parallelism in the memory architecture.
3Productivity
If simultaneous operations across multiple blocks are enabled, then productivity increases, but voltage distribution management becomes more difficult
Solution Approach 1:
The memory device is divided into multiple independently controllable blocks, each with its own set of word lines and select gate lines controlled by dedicated drivers. This segmentation allows simultaneous operations in different blocks without voltage interference, as each segment can be independently voltage-controlled. The third driver specifically manages voltage distribution across blocks during simultaneous operations, simplifying the overall voltage management through modular segmentation.
4Reliability
If precise voltage control across multiple word lines is implemented, then data integrity improves, but the number of required circuit components increases
Solution Approach 1:
Multiple control functions are merged into integrated driver circuits that can control multiple word lines and select gate lines simultaneously. The first, second, and third drivers are designed to combine multiple control tasks, reducing the total number of separate components needed. Level shifters are also merged into the driver architecture, creating an integrated voltage control system that maintains data integrity through precise control while minimizing component count through functional consolidation.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes: a memory cell array including a first memory cell, a first word line, a first circuit coupled to the first word line, a first driver used for a write operation and a read operation, a second driver used for an erase operation, and a voltage generator. The first circuit includes: a second circuit capable of electrically coupling the first word line and a first interconnect; a third circuit capable of electrically coupling the first interconnect and a second interconnect; a fourth circuit capable of electrically coupling the second interconnect and the first driver in the write and read operations; and a fifth circuit capable of electrically coupling the second interconnect and the second driver in the erase operation.