Semiconductor Memory Device Voltage Generation Circuit Segmentation

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Solution Overview

Problem

Current semiconductor memory devices face challenges in achieving uniform and high-speed operation across multiple memory planes due to varying wiring resistances and potential issues with leakage currents, especially when executing read and write operations simultaneously on multiple planes.

Innovation Solution

The semiconductor memory device incorporates a voltage generation circuit connected to word lines via a current path including equalizer regions and voltage supply lines, which reduces wiring resistance and minimizes voltage variations, ensuring consistent operation speed and reducing the impact of bad blocks on normal memory blocks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a voltage generation circuit is connected to word lines via long wirings to serve multiple memory cell arrays, then the circuit can support multiple memory planes, but the wiring resistance increases causing non-uniform operation speed and leakage current issues

Engineering Contradiction:

Improvesupport for multiple memory planesVSAvoidoperation speed uniformity

Core Design Contradiction:

Adaptability or versatilityVSSpeed

Solution Approach 1:

The voltage generation circuit is divided into multiple independent voltage generation units, each serving a specific memory cell array. This segmentation eliminates the need for long shared wirings between the voltage generation circuit and different memory planes, reducing wiring resistance and ensuring uniform operation speed across all memory planes while maintaining support for multiple memory planes.

Inventive Principle:

Principle #1Segmentation

2Adaptability or versatility

If long wirings are used to connect the voltage generation circuit to word lines across multiple memory planes, then multiple memory planes can be accessed, but leakage current increases affecting data reliability

Engineering Contradiction:

Improvemulti-plane access capabilityVSAvoiddata control reliability

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

By segmenting the voltage generation circuit into multiple independent units distributed across different memory cell arrays, the patent eliminates long shared wirings that cause leakage current. Each voltage generation unit is closely connected to its corresponding memory cell array, ensuring reliable data control while maintaining multi-plane access capability.

Inventive Principle:

Principle #1Segmentation

3Device complexity

If the voltage generation circuit is placed far from memory cell arrays to share resources, then device complexity is reduced, but wiring resistance causes non-uniform voltage distribution

Engineering Contradiction:

Improvecircuit configuration simplicityVSAvoidvoltage distribution uniformity

Core Design Contradiction:

Device complexityVSStability of the object's composition

Solution Approach 1:

The voltage generation circuit is segmented into multiple independent voltage generation units, with each unit integrated close to its corresponding memory cell array. This segmentation maintains voltage distribution uniformity by eliminating long wirings while keeping device complexity manageable through modular design.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent transitions from a centralized voltage generation circuit (single-point architecture) to a distributed architecture where multiple voltage generation units are spatially distributed across different memory cell arrays. This dimensional change in circuit architecture ensures uniform voltage distribution while supporting multiple memory planes.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS11862293B2Semiconductor memory device for reducing effect of leakage current

Publication Date: 2024.01.02 KIOXIA CORP

AI summary

A semiconductor memory device includes memory cell arrays including a first memory cell and a first word line connected to the first memory cell, a first wiring electrically connected to the first word lines corresponding to the memory cell arrays, a driver circuit electrically connected to the first wiring, second wirings electrically connected to the first wiring via the driver circuit, a voltage generation circuit including output terminals disposed corresponding to the second wirings, and first circuits disposed corresponding to the memory cell arrays. The voltage generation circuit is electrically connected to the first word lines via a first current path including the second wirings, the driver circuit, and the first wiring. The voltage generation circuit is electrically connected to the first word lines via a second current path including the second wirings and the first circuits and without including the driver circuit.