Semiconductor Memory Voltage Sequencing for Current Variability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor memory devices face challenges in efficiently adjusting operating conditions to optimize threshold voltage control and current flow variability during programming operations, leading to variations in memory cell performance and potential delays in data storage.
Innovation Solution
The method involves a specific sequence of voltage applications to the conductive layers and semiconductor layers, including a write pass voltage, program voltage, and verify voltage, to adjust the current flow and threshold voltages, reducing variability and enhancing operational speed by accumulating electric charges in targeted areas of the electric charge accumulating film.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional programming operations are used, then memory cells can be programmed, but current flow variability among semiconductor layers causes programming delays and reduced efficiency
Solution Approach 1:
The patent applies local quality by differentiating voltage application across different conductive layers. Specifically, the second conductive layer receives a first voltage while the third conductive layer receives a second voltage, creating localized voltage conditions optimized for reducing current flow variability in specific regions of the memory device structure
Solution Approach 2:
The patent changes the voltage parameter applied to different conductive layers during programming operations. By supplying different voltages to the second and third conductive layers, the system adjusts electrical parameters to control current flow distribution and reduce variability among semiconductor layers, thereby improving programming efficiency
2Reliability
If multiple verify steps are performed to ensure programming accuracy, then programming reliability is improved, but operation time increases
Solution Approach 1:
The patent implements feedback through verify operations that check programming results. The system performs verify steps to assess whether programming was successful and uses this information to determine whether additional programming cycles are needed, creating a feedback-controlled process that balances reliability with time efficiency
Solution Approach 2:
The patent applies preliminary action by performing verify operations during the programming sequence to check programming status early. This allows the system to detect programming completion or failures sooner rather than waiting for all possible programming cycles to complete, thereby reducing overall operation time while maintaining reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces current flow variability among semiconductor layers, allowing for faster programming operations and potentially omitting verify steps, thereby improving the efficiency and speed of semiconductor memory devices.
Implementation Method 1
an electric charge accumulating layer disposed between the plurality of first conductive layers and the plurality of first semiconductor layers
Data Source
AI summary
A method of adjusting operating conditions includes: a substrate; first conductive layers; a first semiconductor layers facing the first conductive layers; a second semiconductor layer connected to the first semiconductor layers; and an electric charge accumulating layer disposed between the first conductive layers and the first semiconductor layers. At a predetermined timing of a program operation, the second conductive layer which is one of the first conductive layers is supplied with a program voltage or a write pass voltage. The method executes: a first operation that supplies the second conductive layer with the write pass voltage and supplies a third conductive layer which is one of the plurality of first conductive layers with the program voltage; and a second operation that supplies the second conductive layer with a verify voltage and supplies the third conductive layer with a voltage.