Memory Read Voltage Calibration for Temporal Voltage Shift
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The phenomenon of slow charge loss (SCL) in memory cells leads to temporal voltage shift (TVS), causing threshold voltage changes over time, which affects the accuracy of read operations in memory sub-systems, especially due to die-to-die variation, temperature, and program erase cycles.
Innovation Solution
Tracking and refreshing state metrics by grouping memory partitions into families and associating them with bins, applying bin-specific read offsets to compensate for temporal voltage shifts, and periodically recalibrating these associations to minimize read errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If memory cells are used to store data over time, then data retention is achieved, but temporal voltage shift occurs causing read errors
Solution Approach 1:
The system performs preliminary calibration operations to establish baseline read voltage levels and state metrics before normal read operations begin. This preliminary characterization of memory partition behavior enables the system to compensate for subsequent temporal voltage shifts during data retention periods.
Solution Approach 2:
The system continuously monitors state metrics including read errors and temporal voltage shift characteristics, then feeds this information back to dynamically adjust read voltage offsets. This closed-loop feedback mechanism allows the system to maintain read accuracy despite voltage drift over time during data retention.
2Measurement precision
If read voltage levels are adjusted to compensate for temporal voltage shift, then read accuracy improves, but additional calibration operations increase system complexity
Solution Approach 1:
The calibration system is segmented into discrete, manageable components: state metric collectors that gather specific parameters, calibration engines that process subsets of memory partitions, and offset application modules that adjust voltages. This segmentation allows complex calibration functionality to be implemented through modular, independent units.
Solution Approach 2:
The memory sub-system performs self-calibration by automatically monitoring its own state metrics and adjusting its own read voltage levels without requiring external intervention. The calibration engine uses internally collected data about temporal voltage shift and read errors to autonomously optimize read operations.
3Measurement precision
If comprehensive state metrics are tracked for all memory partitions, then temporal voltage shift compensation accuracy improves, but memory overhead and processing time increase
Solution Approach 1:
The system performs calibration operations on a partial basis, selecting representative subsets of memory partitions for detailed state metric collection and calibration rather than processing every partition exhaustively. This partial action approach achieves sufficient compensation accuracy while reducing processing time and resource overhead.
Solution Approach 2:
State metric collection and calibration operations are performed periodically at scheduled intervals rather than continuously for all memory partitions. This periodic action allows the system to balance compensation accuracy with processing time constraints by updating calibration data at optimal intervals based on observed temporal voltage shift rates.
Data Source
AI summary
Disclosed is a system that comprises a memory device and a processing device, operatively coupled with the memory device, to perform operations that include, responsive to detecting a triggering event, selecting a family of memory blocks of the memory device, the selected family being associated with a set of bins, each bin associated with a plurality of read voltage offsets to be applied to base read voltages during read operations. The operations performed by the processing device further include calibration operations to determine data state metric values characterizing application of read voltage offsets of various bins. The operations performed by the processing device further include identifying, based on the determined data state metrics, a target bin and associating the selected family with the target bin.