Nonvolatile Memory Cell Array Voltage Shift Equalization
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Solution Overview
Problem
Nonvolatile memory devices, particularly flash memory devices, face challenges in achieving balanced write speeds due to differences in minimum physical voltage shifts during data write operations, leading to inefficiencies and potential damage from uneven voltage shifts during miniaturization.
Innovation Solution
The implementation of a nonvolatile memory device with a data memory cell array divided into two groups, a write sequence memory cell array, and a write time memory cell array, along with a control circuit that manages the allocation of data and voltage distributions to equalize shifts in minimum physical voltages, allowing for optimized write speed and preventing damage by controlling the voltage ranges and sequences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is written to memory cells using conventional programming sequences, then multi-level data storage is achieved, but write speed varies significantly depending on the programming sequence due to differences in minimum physical voltage shifts
Solution Approach 1:
The memory cell array is divided into two groups (first group and second group) that are programmed independently. This segmentation allows the system to manage voltage shifts separately for each group, ensuring consistent write speed regardless of the overall programming sequence. The data to be written is also divided into first data and second data corresponding to each group.
Solution Approach 2:
The control circuit determines the programming sequence in advance by comparing minimum physical voltage shifts. It identifies which group should be programmed first based on voltage shift characteristics, and pre-configures the programming sequence to optimize write speed consistency. This preliminary determination prevents write speed variation before the actual programming occurs.
2Quantity of substance
If process miniaturization is applied to increase storage capacity, then memory density improves, but minimum physical voltage shifts cause errors and damage in memory cells
Solution Approach 1:
By dividing the memory cell array into two groups and programming them separately, the system reduces the cumulative voltage shift impact on individual cells. Each group experiences smaller voltage shifts during programming, preventing damage that would occur in miniaturized cells subjected to larger voltage variations.
Solution Approach 2:
The control circuit dynamically adjusts programming parameters based on minimum physical voltage shift characteristics. By monitoring and responding to voltage shift parameters, the system prevents harmful voltage variations from damaging miniaturized memory cells while maintaining high storage capacity.
3Speed
If programming sequence is optimized for maximum write speed in one direction, then write speed increases for that sequence, but average write speed across all sequences does not improve significantly
Solution Approach 1:
The control circuit dynamically determines the programming sequence based on the actual data to be written and voltage shift characteristics. Rather than using a fixed sequence, the system adapts the programming order (first group then second group, or vice versa) to maintain optimal write speed for each specific operation, thereby improving average write speed across all programming scenarios.
Data Source
AI summary
A nonvolatile memory device includes a data memory cell array having multi level memory cells divided into two groups, a write sequence memory cell array configured to store a write sequence indicating in which of the two groups the multi level data was written first, and a write time memory cell array configured to store the number of write operations performed on the memory cells. The memory device further includes a control circuit configured to control a program operation by determining allocation of data corresponding to a minimum physical voltage distribution causing a reaction of the memory cells, such that a shift of a first minimum physical voltage causing a reaction due to the first write operation and a shift of a second minimum physical voltage causing a reaction due to the second write operation are equal regardless of write sequence.