Nonvolatile Memory Programming Voltage Skipping
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Solution Overview
Problem
Conventional nonvolatile memory devices face challenges with programming errors due to electrical interference between adjacent memory cells, particularly in multi-level cell (MLC) devices, which affects storage capacity and reliability.
Innovation Solution
The implementation of a nonvolatile memory device with a voltage generator and control logic component that applies a series of program and verification voltages to memory cells, skipping voltages for successfully programmed states in subsequent iterations to reduce interference and increase efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional programming methods are used for MLC devices, then storage capacity is increased, but programming errors occur due to electrical interference between adjacent memory cells
Solution Approach 1:
The programming operation is divided into multiple sequential program loops, each targeting specific logic states. Within each loop, verification operations are performed to determine if programming is complete, allowing the system to segment the programming process into manageable stages that reduce interference effects.
Solution Approach 2:
The patent employs periodic program loops with alternating programming and verification phases. This periodic action allows the system to apply programming voltages, verify results, and adjust subsequent programming actions based on verification outcomes, thereby reducing cumulative electrical interference.
2Reliability
If multiple program voltages are applied in each loop iteration, then programming completeness is ensured, but power consumption increases
Solution Approach 1:
Verification operations provide feedback on the programming status of memory cells. Based on this feedback, the control logic determines whether additional program voltages are necessary or if programming can be terminated early, optimizing power consumption while ensuring completeness.
Solution Approach 2:
The patent dynamically adjusts programming parameters including voltage levels, pulse widths, and timing based on verification results. This adaptive parameter adjustment allows the system to minimize power consumption by applying only the necessary programming effort required to achieve complete programming.
3Reliability
If all program voltages are applied in every loop iteration, then programming reliability is maintained, but programming time increases
Solution Approach 1:
Verification operations are performed preliminarily within each program loop to assess programming status before proceeding to the next iteration. This preliminary verification allows the system to skip unnecessary program voltage applications in subsequent loops, reducing total programming time while maintaining reliability.
Solution Approach 2:
The patent applies program voltages selectively based on verification results rather than applying all voltages in every loop. This partial action approach applies only the necessary programming effort required, avoiding excessive programming operations that would increase time without adding value.
4Measurement precision
If verification operations are performed for each logic state, then programming accuracy is improved, but device complexity increases
Solution Approach 1:
The verification circuit and control logic are designed to universally handle multiple logic states through a standardized verification process. This multi-functional design allows the same verification mechanism to be applied across different logic states, improving accuracy without proportionally increasing device complexity.
Solution Approach 2:
The control logic selectively activates verification operations based on programming progress and requirements. Verification resources are discarded (not activated) when programming is clearly complete or when verification is unnecessary, and recovered (activated) when needed, optimizing the balance between accuracy and complexity.
Data Source
AI summary
A nonvolatile memory device comprises a memory cell array comprising a plurality of memory cells, a voltage generator configured to generate voltages to program the plurality of memory cells, and a control logic component configured to control the voltage generator to provide a plurality of program voltages to selected memory cells during successive iterations of a program loop. Wherein where memory cells corresponding to one logic state are judged to be program passed during a current iteration of the program loop, the control logic component controls the voltage generator such that a program voltage corresponding to the one logic state is skipped during subsequent iterations of the program loop.